JPH05267583A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To vary the value of resistance of a semiconductor resistive element without changing a wiring pattern and the concentration of a diffused impurity. CONSTITUTION:Contact electrodes 4, 5 are formed in MOS transistor composed of source-drain regions 1, 2 and gate 8 formed of polysilicon and are short- circuited by an aluminum wiring 3. Further, a contact electrode 6 independent from the contact electrodes 4, 5 is formed and an aluminum wiring 7 is connected with the electrode 6. Thus, the value of resistance of a semiconductor resistive element is varied when only the applied voltage of the gate 8 is changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device provided with a semiconductor resistance element whose resistance value is variable.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit device, when it is necessary to adjust the resistance value, a plurality of semiconductor resistance elements are connected by wiring.

FIGS. 5 (a) and 5 (b) are plan views before and after using a wiring pattern of a semiconductor resistance element for explaining a conventional example, respectively. As shown in FIG. 5A, a plurality of resistors made of a P-type or N-type impurity diffusion region or a polysilicon layer in which P-type or N-type impurities are diffused before the resistance value adjustment of the conventional semiconductor resistance element are performed. 20, a contact 21 provided at both ends of the resistor 20, and a contact 21
And the wiring 22 connected to. Next, FIG.
As shown in (b), the wiring 2 is used to adjust the resistance value.
By adding 3 and connecting between the plurality of resistors 20, a resistor having a resistance value smaller than the resistance value of the configuration shown in FIG. 5A can be obtained.

Assuming that the two resistors 20 are the same, the resistance value of the structure of FIG. 5 (b) is half that of the structure of FIG. 5 (a). Further, the resistance value of one resistor 20 can be changed by the impurity concentration in the semiconductor region forming this resistor 20.

[0005]

In the above-described conventional semiconductor integrated circuit device, particularly the semiconductor resistance element, when the resistance value is changed, the wiring pattern connecting a plurality of resistors is changed or the resistors are changed. The impurity concentration of must be changed. Therefore, the conventional semiconductor integrated circuit device having the semiconductor resistance element has a drawback that the resistance value cannot be changed without redesign.

An object of the present invention is to provide a semiconductor integrated circuit device capable of easily changing the resistance value of such a semiconductor resistance element.

[0007]

A semiconductor integrated circuit device according to the present invention comprises a P-type or N-type source region and a drain region forming a P-channel or N-channel field effect transistor, and the P-type or N-type field effect transistor. A channel region sandwiched by an N type source region and a drain region and having a conductivity type opposite to that of the P type or N type source region and the drain region, and formed on the channel region to invert the channel region. A gate electrode formed via an oxide film on the channel region, the source region and the drain region, a first contact electrode provided on one of the source region and the drain region, and the first contact electrode The drain region or the drain region formed by sandwiching the source region or the drain-in region and the channel region. The source region includes a second contact electrode formed in a number corresponding to the number of the first contact electrodes provided in the source region, and a wiring connecting at least one of the source region and the drain region to each other. And a drain connecting at least one of each of the drain regions as one terminal, the contact electrode of either the source region or the drain region as the other terminal, and the gate electrode as a resistance value adjusting terminal Is configured.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. 1A and 1B are a plan view of a semiconductor resistance element and an equivalent circuit diagram thereof for explaining an embodiment of the present invention. As shown in FIG. 1A, in this embodiment, a source / drain region 1 and a source / drain region 2 are formed in an N-type silicon substrate (not shown), and these source / drain regions 1 and 2 are formed on one end of the source / drain region 1. Contact electrodes 4 and 5 connected by aluminum wiring 3 are provided. Further, a contact electrode 6 is provided on one end of the source / drain region 2 opposite to the contact electrode 5, and an aluminum wiring 7 is connected thereto. On the other hand, a polysilicon gate 8 is provided on the channel region between the source / drain regions 1 and 2 with the oxide film interposed therebetween. The gate 8 is connected to the aluminum wiring 10 by the contact electrode 9.

Next, as shown in FIG. 1B, an equivalent circuit of such a semiconductor resistance element is shown in a simplified manner.
Here, three partial resistors 11, three partial MOS transistors 12 and three partial resistors 13 are shown.
First, when a voltage is applied between the aluminum wirings 3 and 7 while a low level voltage is applied to the aluminum wiring 10, the channel immediately below the polysilicon gate 8 is closed. That is, since the partial MOS transistor 12 is off, the current flows through the source / drain region 2, that is, the partial resistance 11 in the equivalent circuit. This partial resistance 1
If the resistance value of 1 and the resistance value of the partial resistance 13 are equal to R, the resistance value of the semiconductor resistance element is 3R. Next, when a high level voltage is applied to the aluminum wiring 10, the channel directly below the polysilicon gate 8 is opened. That is, since the partial MOS transistor 12 in the equivalent circuit is turned on, the current flows in the source / drain regions 1 and 2
Middle resistance, that is, partial resistance 11 and partial resistance 13 in the equivalent circuit
Flowing through. At this time, the resistance value of the semiconductor resistance element is 1.5.
It becomes R. In short, by changing the potential of the polysilicon gate 8, the resistance value between the aluminum wirings 3 and 7 changes between 1.5R and 3R.

FIG. 2 shows the MOS shown in FIGS. 1 (a) and 1 (b).
It is a current / voltage characteristic view of a transistor. As shown in FIG. 2, even if the gate voltage V _G is increased in an actual MOS transistor, the drain current I _D exhibits a current-voltage characteristic having a finite value determined by the source-drain voltage V _SD. .. That is, it works as an equivalent resistance even when the MOS transistor is on.

3A and 3B are a plan view of a semiconductor resistance element and an equivalent circuit diagram thereof for explaining another embodiment of the present invention. As shown in FIG. 3A, this embodiment is different from the above-mentioned embodiment in that the positions and shapes of the contact electrodes 5 and 14 and 15 on the source / drain regions 1 and 2 and the aluminum wirings 3, 7 and 10 are different. The pattern is changed. In addition, 19 represents the distance between contacts.

As shown in FIG. 3 (b), the equivalent circuit of FIG. 3 (a) is shown in a simplified form.
It is represented by an OS transistor 17, an equivalent resistance 18, and a source / drain region resistance 16. First, when a low level voltage is applied to the aluminum wiring 10, since the effective MOS transistor 17 is off, the resistance value appearing between the aluminum wirings 3 and 7 varies depending on the distance 19 between contacts. Area resistance 16
It becomes the value of. This resistance value is R ₁ . Next, when a high level voltage is applied to the aluminum wiring 10, the effective M
Since the OS transistor 17 is turned on, its on resistance 1
When the resistance value of 8 is R _ON , the resistance value appearing between the aluminum wirings 3 and 7 is

[0013]

[0014] That is, the aluminum wiring 10
The resistance value that appears between the aluminum wirings 3 and 7 depends on the voltage applied to

[0015]

Varies between.

FIG. 4 shows the MOS in FIGS. 3 (a) and 3 (b).
It is a characteristic view showing the mode of resistance value change by the gate voltage of a transistor. As shown in FIG. 4, this characteristic shows a change in the resistance value with a change in the gate voltage of the aluminum wiring 10. In this embodiment, the current when the MOS transistor is turned on is approximately equal to the on-current of the MOS transistor whose gate width is the opposing length of the contact electrodes 14 and 15, and the estimation is simple, and an easy and stable design can be realized.

[0018]

As described above, the semiconductor integrated circuit device of the present invention uses the structure of the MOS transistor as the semiconductor resistance element to change the impurity concentration of the semiconductor substrate or the wiring pattern. Instead, there is an effect that the resistance value can be changed only by changing the gate voltage.

[Brief description of drawings]

FIG. 1 is a diagram showing a plane of a semiconductor resistance element and its equivalent circuit for explaining an embodiment of the present invention.

FIG. 2 is a current / voltage characteristic diagram of the MOS transistor in FIG.

FIG. 3 is a diagram showing a plane of a semiconductor resistance element and its equivalent circuit for explaining another embodiment of the present invention.

FIG. 4 is a characteristic diagram showing a state of resistance change according to a gate voltage of the MOS transistor in FIG.

FIG. 5 is a plan view before and after using a wiring pattern of a semiconductor resistance element for explaining a conventional example.

[Explanation of symbols]

 1, 2 source / drain regions 3, 7, 10 aluminum wiring 4 to 6, 9, 14, 15 contact electrode 8 polysilicon gate 11, 13 partial resistance 12 partial MOS transistor 16 source / drain region resistance 17 effective MOS transistor 18 equivalent Resistance 19 Distance between contacts

Claims (1)

[Claims] 1. A P-type or N-type source region and a drain region forming a P-channel type or N-channel type field effect transistor, and being sandwiched between the P-type or N-type source region and the drain region, and A channel region having a conductivity type opposite to that of the P-type or N-type source region and the drain region, and formed on the channel region to invert the channel region and on the channel region and the source region and the drain region. A gate electrode formed through an oxide film, a first contact electrode provided in one of the source region and the drain region, the source region or drain-in region provided with the first contact electrode, and the channel The first contact electrode provided in the drain region or the source region formed across the region. A second contact electrode formed according to the number of poles, and a wiring connecting at least one of the source region and the drain region to each other,
The wiring connecting at least one of the source region and the drain region was used as one terminal, and the contact electrode of either the source region or the drain region was used as the other terminal, and the gate electrode was used as a resistance adjusting terminal. A semiconductor integrated circuit device having a semiconductor resistance element.