JP2678092B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a high voltage lateral MOS (metal oxide semiconductor) field effect transistor.

[0002]

2. Description of the Related Art A conventional high breakdown voltage lateral MOS field effect transistor (hereinafter abbreviated as LMOS) will be described below.

FIG. 5 (a) is a plan view of a conventional LMOS, and FIG. 5 (b) is a sectional view taken along the line AB of FIG. 5 (a). The high-concentration drain region 1 is formed in the extended drain region 2,
Further, similarly, it is formed so as to be surrounded by the same conductivity type region 3 (hereinafter, abbreviated as PT region) included in the extended drain region 2 and the silicon substrate 4. A channel portion 5 is formed on the silicon substrate 4 side of the junction between the extended drain region 2 and the silicon substrate 4 on the silicon surface portion, and on the channel portion 5, a gate oxide film 6 and a polysilicon 7 to be a gate electrode are arranged in parallel. It is set up. A source region 8 of opposite conductivity type is formed beside the channel portion 5 opposite to the extended drain region 2, and a channel stopper 9 of the same conductivity type of high concentration is formed so as to surround the source region 8. Has been done. Further, in order to suppress the substrate bias effect of the channel, a high-concentration region 10 of the same conductivity type is provided adjacent to the source region 8 and is electrically connected to the source electrode 11 like the source region 8. In FIG. 5, reference numeral 12 is a drain electrode.

[0004]

In the conventional LMOS, the breakdown current during breakdown passes through the drain electrode 12, the drain region 1, the extended drain region 2, and the silicon substrate 4 under the source region 8 and is the same. It flows through the conductivity type region 10 to the source electrode 11. If the breakdown occurs when the power load of the LMOS is inductive such as a motor or a solenoid, and the breakdown current becomes large, the resistance component of the silicon substrate 4 under the source region 8 causes the extension drain region 2, the silicon substrate 4 , The parasitic bipolar transistor formed in the source region 8 operates, and the LMOS is destroyed due to heat generation.
As described above, the conventional LMOS has a drawback that the reverse safe operation area (hereinafter, abbreviated as RASO) is weak.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having an improved RASO value representing a safe operating region in the reverse direction.

[0006]

The present invention achieves the above object.
Substrate for one conductivity type (for example, p-type)
Reverse conductivity type (n-type) extended drain formed on the surface side of
Lateral field effect transistor having a source region and a source region
With a semiconductor substrate in the extended drain region
A part of the PT region of the same conductivity type (p type) is drain-source
Short in the direction between the source regions, the drain of the source region
・ Almost corresponding to the short PT region in the direction between the source regions
The same conductivity type (p-type) as the semiconductor substrate
In other words, in other words, the corresponding source region (n-type) part is excluded.
I'll leave). In addition, the source region (n type) is half
Same conductivity type (p-type) as conductor board, higher than semiconductor board
It is provided in the degree region (for example, the channel stopper 9).

[0007]

With this structure, the reverse breakdown voltage is determined in the portion where the same conductivity type region is shortened or removed, and the source bipolar region is removed to eliminate the parasitic bipolar
Transistors stop working, resulting in RAS
O value improves.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the LMOS of the present invention will be described in detail below with reference to the drawings.

FIG. 1A shows an L of an embodiment according to the present invention.
1A is a plan view of the MOS, FIG. 1B is a sectional view taken along line AB of FIG. 1A, and FIG. 2A is an LMO of another embodiment according to the present invention.
FIG. 2B is a plan view of S and FIG. 2B is a sectional view taken along the line AB of FIG. 1 and 2, FIG.
The same numbers are given to the same parts as. That is, 1 is a high-concentration drain region, 2 is an extended drain region, 3 is the same conductivity type region as the silicon substrate (hereinafter referred to as PT region),
4 is a silicon substrate, 5 is a channel portion, 6 is a gate oxide film, 7 is polysilicon, 8 is a source region, 9 is a channel stopper, 10 is a high-concentration region of the same conductivity type, 11 is a source electrode, and 12 is a drain electrode. Is shown.

A feature of the present invention is that, as shown in FIG. 1A, the length of the PT region 3 in the portion of the line AB is shorter than that of the other portions. On the other hand, in the conventional product, the length of the PT region is constant as shown in FIG. Therefore, in the present invention, the reverse breakdown voltage between the drain and the source becomes low in the portion of the line AB, and the reverse breakdown voltage of the lateral MOS is determined in the region where the length of the PT region 3 is short. Therefore, by removing the source region 8 of the lateral MOS transistor in which the length of the PT region 3 is shortened, the breakdown current is reduced to the silicon substrate 4 below the source region 8 as in the conventional example.
Since it directly passes through the source electrode 11 without passing through, the parasitic bipolar transistor formed by the extended drain region 2, the silicon substrate 4, and the source region 8 does not operate, and the breakdown of the lateral MOS transistor is suppressed. At this time PT
By changing the length of the region 3, the breakdown voltage of the device can be changed.

Instead of shortening the length of the PT region 3,
The same effect can be expected by removing a part of the PT region 3 as shown by the line AB in FIG.

FIG. 3 shows a RASO level measuring circuit,
FIG. 4 shows a comparison of RASO levels of the conventional product and the product of the present invention. The RASO level of the product of the present invention is about 10 times higher than that of the conventional product. As described above, according to the present invention, the RASO of the process LMOS similar to the conventional one is remarkably improved.

[0013]

As apparent from the above embodiments, according to the present invention, the length of at least a part of the PT region in the drain / source region direction is shorter than the length of the other PT regions. RAS that represents the safe operating area of
A semiconductor device having an improved O value can be provided.

[Brief description of the drawings]

1A is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line AB of FIG. 1A.

2A is a plan view of a semiconductor device according to another embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along the line AB of FIG. 2A.

FIG. 3 is a circuit diagram of a RASO level measurement circuit.

FIG. 4 is a comparison diagram of the RASO level of the conventional product and the product of the present invention.

5A is a plan view of a conventional semiconductor device, and FIG. 5B is a cross-sectional view taken along line AB of FIG. 5A.

[Explanation of symbols]

 1 drain region 2 extended drain region 3 same conductivity type region as silicon substrate 4 silicon substrate 8 source region

Front Page Continuation (72) Hiroyuki Shindo, 1006 Kadoma, Kadoma City, Osaka Prefecture, Matsushita Electric Industrial Co., Ltd. (72) Toshihiko Uno, 1006, Kadoma, Kadoma City, Osaka Prefecture ) Inventor Hideo Kawasaki 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP 4-107787 (JP, A) JP 4-107870 (JP, A) JP JP 4-107867 (JP, A) JP 4-107879 (JP, A) JP 2-170555 (JP, A) JP 63-95672 (JP, A)

Claims (4)

(57) [Claims] 1. A semiconductor substrate of one conductivity type formed on the front surface side.
Lateral with extended drain and source regions of opposite conductivity type
Type MOS field effect transistor, the extended drain region
Part of the PT region of the same conductivity type as the semiconductor substrate in the region
Is short in the direction between the drain and source regions, and
The short PT region in the direction between the drain and source regions of
A portion substantially corresponding to the portion has the same conductivity type as the semiconductor substrate.
Is a semiconductor device. 2. The source region has the same conductivity type as that of the semiconductor substrate.
The semiconductor device according to claim 1, wherein the semiconductor substrate is provided in a higher concentration region than the semiconductor substrate.
The semiconductor device described. 3. Instead of shortening a part of the PT region,
The semiconductor device according to claim 1, wherein the PT region is not formed in the above-mentioned portion.
Place. 4. A high-concentration region of the same conductivity type as the semiconductor substrate is
The semiconductor device according to claim 2, wherein the semiconductor device is extended to a lower portion of the gate electrode.
Place.