JPH04225569A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve a RASO value representing a safety operating region of the opposite direction of a lateral MOS field effect transistor. CONSTITUTION:The length of at least part of a region 3 of the same conductivity type as that of a silicon substrate 4 formed on the surface of an extended drain region 2 in drain source region direction is shorter than that of the same conductivity type region, or instead the region 3 is removed, and the source region of the part is also removed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices such as high voltage lateral MOS (metal oxide semiconductor) field effect transistors.

0002

2. Description of the Related Art A conventional high voltage lateral MOS field effect transistor (hereinafter abbreviated as LMOS) will be explained below.

FIG. 5(a) is a plan view of a conventional LMOS, and FIG. 5(b) is a sectional view taken along line A--B in FIG. 5(a). A highly doped drain region 1 is formed within an extended drain region 2;
Furthermore, it is formed so as to be surrounded by a region 3 of the same conductivity type as the silicon substrate 4 (hereinafter abbreviated as PT region) similarly included in the extended drain region 2 . A channel portion 5 is formed on the silicon substrate 4 side of the junction between the extended drain region 2 and the silicon substrate 4 in the silicon surface portion, and a gate oxide film 6 and a polysilicon 7 serving as a gate electrode are formed on the channel portion 5. It is set up. A source region 8 of the opposite conductivity type is formed next to the channel portion 5 so as to face the extended drain region 2, and a channel stopper 9 of the same conductivity type with high concentration is formed to surround the source region 8. has been done. Furthermore, in order to suppress the substrate bias effect of the channel, a high concentration region 10 of the same conductivity type is provided adjacent to the source region 8 and is electrically connected to the source electrode 11 similarly to the source region 8 . In addition, in FIG. 5, 12 is a drain electrode.

0004

[Problems to be Solved by the Invention] In the conventional LMOS, the breakdown current at the time of breakdown passes from the drain electrode 12 through the drain region 1, the extended drain region 2, and the silicon substrate 4 under the source region 8. It flows through the conductivity type region 10 to the source electrode 11 . When the power load of the LMOS is inductive, such as a motor or a solenoid, breakdown occurs, and when the breakdown current becomes large, the extended drain region 2, silicon substrate 4 due to the resistance component of the silicon substrate 4 under the source region 8
, the parasitic bipolar transistor formed in the source region 8 operates, and the LMOS is destroyed due to heat generation. In this way, the conventional LMOS has a safe operating area (
Hereinafter, it will be abbreviated as RASO. ) was weak.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device with an improved RASO value representing a safe operation area in the reverse direction.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above objects, the present invention provides a silicon substrate having a same conductivity type contained in an extended drain region of an opposite conductivity type existing on a silicon substrate having a surface. of at least a portion of the conductivity type region;
A structure in which the length in the drain/source region direction is made shorter than the length of other regions of the same conductivity type and the source region of the lateral MOS transistor is removed, or at least a part of the region of the same conductivity type is removed. The configuration is such that the source region of the lateral MOS transistor is also removed.

[0007]

[Operation] With this configuration, the reverse breakdown voltage is determined by the shortened or removed portion of the same conductivity type region, and by removing the source region in that portion, the parasitic bipolar
The transistor becomes inoperable, resulting in RAS
O value improves.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of an LMOS according to the present invention will be described in detail below with reference to the drawings.

FIG. 1(a) shows L of an embodiment according to the present invention.
A plan view of the MOS, FIG. 1(b) is a sectional view taken along the line A-B in FIG. 1(a), and FIG. 2(a) is an LMO of another embodiment according to the present invention.
A plan view of S, FIG. 2(b) shows a sectional view taken along the line AB in FIG. 2(a). In FIGS. 1 and 2, FIG. 5 of the conventional example
The same parts are given the same numbers. That is, 1 is a high concentration drain region, 2 is an extended drain region, 3 is a region of the same conductivity type as the silicon substrate (hereinafter referred to as PT region),
4 is a silicon substrate, 5 is a channel part, 6 is a gate oxide film, 7 is polysilicon, 8 is a source region, 9 is a channel stopper, 10 is a high concentration region of the same conductivity type, 11 is a source electrode, 12 is a drain electrode It shows.

A feature of the present invention is that, as shown in FIG. 1(a), the length of the PT region 3 is shorter in the portion along line A-B than in other portions. On the other hand, in the conventional product, the length of the PT region is constant as shown in FIG. Therefore, in the present invention, the reverse breakdown voltage between the drain and the source is lower at the line A-B, and the reverse breakdown voltage of the lateral MOS is lower in the PT region 3.
The length of is determined by the short region. Therefore, by removing the source region 8 of the lateral MOS transistor in which the length of the PT region 3 is shortened, the breakdown current flows directly to the source electrode without passing through the silicon substrate 4 under the source region 8 as in the conventional example. 11, the parasitic bipolar transistor formed by the extended drain region 2, silicon substrate 4, and source region 8 does not operate, and the lateral M
Destruction of the OS transistor is suppressed. At this time, by changing the length of the PT region 3, it is possible to change the breakdown voltage of the element.

[0011] Also, instead of shortening the length of the PT region 3,
A similar effect can be expected by removing part of the PT region 3 as shown in the line A-B in FIG. 2(a).

FIG. 3 shows a RASO level measurement circuit,
FIG. 4 shows a comparison of the RASO levels of the conventional product and the product of the present invention. The RASO level of the product of the present invention is approximately 10 times higher than that of the conventional product. As described above, according to the present invention, the RASO of a conventional process LMOS is significantly improved.

[0013]

As is clear from the above embodiments, according to the present invention, since the length of at least a part of the PT region in the drain/source region direction is shorter than the length of the other PT regions, RAS representing the safe operating area of
A semiconductor device with improved O value can be provided.

[Brief explanation of the drawing]

FIG. 1 (a) is a plan view of a semiconductor device according to an embodiment of the present invention (b)
is a cross-sectional view taken along line A-B in Figure 1(a).

FIG. 2(a) is a plan view of a semiconductor device according to another embodiment of the present invention; FIG.
) is a cross-sectional view taken along line A-B in Figure 2(a).

[Figure 3] Circuit diagram of RASO level measurement circuit

[Figure 4] Comparison diagram of RASO level between conventional product and inventive product

[Figure 5] (a) is a plan view of a conventional semiconductor device (b) is a cross-sectional view taken along line A-B in Fig. 5(a).

[Explanation of symbols]

1 Drain region 2 Extended drain region 3 Region of the same conductivity type as the silicon substrate 4 Silicon substrate 8 Source region

Claims (4)

[Claims] 1. A silicon substrate, an extended drain region of a conductivity type opposite to that of the silicon substrate formed on a surface of the silicon substrate, and a region of the same conductivity type as the silicon substrate formed on a surface of the extended drain region. In a semiconductor device constituted by a plurality of lateral MOS field effect transistors having at least A semiconductor device characterized in that the length of the region is shorter than that of other regions of the same conductivity type. [Claim 2] Horizontal MOS in which the length of the same conductivity type region is short.
2. The semiconductor device according to claim 1, wherein a source region of the field effect transistor is removed. 3. The semiconductor device according to claim 1, wherein instead of shortening the length of the same conductivity type region, that portion of the same conductivity type region is removed. 4. The semiconductor device according to claim 3, wherein a source region of a lateral MOS field effect transistor is removed from which a region of the same conductivity type is removed.