JPS6221262A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To adjust timing simply, by arranging timing adjusting elements comprising a capacitor and resistors on a plurality of chips, and performing connection and cutting of these elements and circuits by changing a small number of mask patterns. CONSTITUTION:Resistor elements 5 comprising P-type diffused regions are formed on the surface of a substrate 1 in a wiring region, where Al wires are provided, in a comb shape. A capacitor forming electrode 8 comprising poly Si forms a gate capacitor on an oxide film in the wiring region. The Al wires in regions 30 and 31 shown by broken lines are cut. The Al wire in a broken region 32 is connected. The mask of the Al wires is changed so that the above described connection and cutting are obtained. Thus, the resistor elements comprising the P-type diffused regions and the capacitor element comprising the gate capacitor of a P-channel transistor are connected to the output node of an inverter circuit. In this way, the delay amount is made large.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit device having a delay circuit.

(b) Conventional technology LI! In I-engineering design, since the chip area of capacitive elements and resistive elements is to be reduced, it is usual that only those elements essential to the system are pattern-designed.

However, such a design method has the disadvantage that, after a test diagnosis, when a circuit is modified in response to a design change or an error occurs, the modification must be made in a large scale.

Furthermore, it is known that it is difficult to form a transistor element in a wiring region or an electric wire region.

This is described, for example, on page 66 of IEICE 5EID84-72 Simulator 0ADDIIiT edition.
This is because if the source/drain contacts of the MOE+ transistor are sufficiently connected, the channel conductance of the MOE+ transistor will be modulated. This is shown in Figure 2, Figure 4, and Factor 5.

An example in which complementary MOB inverter circuits are formed in a wiring area and a power line area will be described.

The fourth factor is a top view, FIG. 5 is a sectional view of the main part of FIG. 4, and FIG. 2 is an equivalent circuit diagram.

In these figures, ←! ! (49--The overall average is aluminum wiring, the decoy alpha power is a power line cut out with aluminum wiring, the main line is VDD line, (471 is Vs4 * (51) is formed on an N-type substrate. P-type Riel area, (52
) (52) is a P-type diffusion region which becomes a source main drain region, and (53) (53) is an N-type diffusion region which also becomes a source or drain region. (54) is a gate electrode formed of polysilicon, (56) is a buried oxide film, (
57) is a dirt oxide film, and (58) is an interlayer insulating film.

(The barrel is a P-channel MOS transistor and an N-channel MO8) Aluminum wiring connects each drain of the transistor, (60) is a contact hole connecting aluminum wiring (441 and polysilicon), (61) or 64
) are contact holes connecting the aluminum wiring and each diffusion region.

Note that the wiring (the cheeks correspond to the nodes of the inverter circuit in Figure 2).

As is clear from FIG. 4, when a transistor is formed in this wiring area (some of which are MOS transistors in the power supply area), there is a problem in that the source/drain contacts are not sufficient and the channel conductance is modulated.

(c) Problems to be Solved by the Invention The present invention provides a semiconductor integrated circuit device having a delay circuit, and when the timing correction of the delay circuit after test diagnosis can be performed using only capacitive elements and resistive elements, It is an object of the present invention to make it possible to correct timing by changing a small number of masks without increasing the amount of noise.

B.) Third Means for Solving the Problems First, the present invention provides a semiconductor integrated circuit device having a delay circuit, in which a large number of timing adjustment elements including capacitance elements and resistance elements are disposed in a wiring area or a power supply line area. The timing adjustment device is characterized in that the timing is adjusted by appropriately connecting or disconnecting the timing adjusting element.

(E) Effect According to the invention, since a large number of capacitors and resistors are arranged on the chip in advance, timing adjustment after test diagnosis can be performed using only capacitors and resistors.# For C, the above-mentioned capacitive element and resistive element can be used for this modification, making the modification extremely simple.Also, the capacitive element and resistive element for adjustment can be placed in an area where no transistor is formed on the chip. If this is done, the chip area will not increase.

(F) Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 to 3. Tree - An example is an input 2771 provided in a peripheral circuit such as a static type semiconductor memory or a dynamic type semiconductor memory.
It is used for timing correction, etc. in delay circuits such as circuits.

FIG. 1 is a top view when a capacitive element and a resistive element are used as delay elements.

In FIG. 1, (l) is an N-type semiconductor substrate, and ]2) is an n7tP-type quell region formed on the full surface of this substrate.

(3) FltP channel M formed on the surface of the substrate (11)
P becomes the source and drain regions of the OS transistor.
The type diffusion region, (4) is formed in the felt region (2)n)t
N-channel cell O8) This is an N-type diffusion region that becomes the source and drain regions of a transistor. (5) is a resistance element consisting of a P-type diffusion region formed in a comb shape on a substrate Illll in a wiring area where aluminum wiring, which will be described later, is thrown;
) is a P-type impurity region formed on the surface of the substrate f11 in the wiring region and having a t-gate capacitance. (7) is a gate electrode made of NTT polysilicon placed on the gate oxide film, and (8) is a capacitance forming electrode made of polysilicon that forms a dirt capacitance and is placed on the oxide film in the wiring region. The resistance element (5
) and electrode wiring consisting of nt aluminum electrodes placed on the ffi element (8).

Connect to memory cells and other peripheral circuits. αdαη is a power supply wiring consisting of n, 7t aluminum electrodes placed through the same interlayer insulating film, and a- is VDD l! Power line αη
uvatsW1[! The aluminum electrode connects the respective drains of both transistors, and the contact hole connects the polysilicon and aluminum electrode.
22 to □□□ are contact holes connecting the diffusion region and the aluminum electrode.

Note that the electrode a41CL5 corresponds to the node≠ of the inverter circuit in FIG.

In this way, the inverter circuit shown in FIG. 2 is formed, and the resistive element 51 and the capacitive element (8) are formed in the wiring area, so that the chip area does not become large.

After testing and diagnosing a semiconductor integrated circuit device that uses peripheral circuits configured in this manner, the predetermined timing cannot be obtained and it is necessary to increase the delay of the input circuit.

In such a case, in this embodiment, a resistive element and a capacitive element are connected as shown in the equivalent circuit of FIG.

A resistive element and a capacitive element are connected. That is, the mask for the aluminum wiring is improved so that the aluminum wiring between the areas indicated by the broken lines in FIG. 1 is broken, and the aluminum wiring in the broken area G is connected. By improving the mask in this way, a resistive element made of a P-type diffusion region and a capacitive element made of the gate capacitance of a P-channel transistor are connected to the output node of the inverter circuit to increase the delay.

As mentioned above, when used as a transistor, it is necessary to have sufficient contact between the source/drain and the metal so that the channel conductance does not change again, but when used as a capacitive element, there must be sufficient contact between the diffusion layer and the power supply line. Since the number of contacts may be relatively small, a capacitive element can be easily formed even in a region where a large amount of metal is patterned, such as a wiring region.

one! In this embodiment, the gate capacitor is used as the capacitor, and the diffused resistor is used as the resistor, but the value is not limited to n.

(g) Detailed explanation of the invention As a reminder, according to the invention, the timing adjustment element consisting of a capacitive element and a resistive element can be connected or disconnected from a circuit by changing the pattern of a small number of masks. Since the timing adjustment elements are placed on the chip in advance, even if there is a correction after test diagnosis, these elements can be used and the correction can be made with a small number of mask changes, making the correction very simple. Moreover, if these adjustment elements are placed in the wiring area, the increase in chip area can be reduced to 1/1°.

[Brief explanation of drawings]

FIG. 1 is a top view showing an uninvented embodiment, FIGS. 2 and 3 are equivalent circuit factors in the configuration shown in FIG. 1, and FIG. FIG. 5 is a sectional view of the main part of FIG. 4. fllfi - one semiconductor substrate, F21 (51) - Fell region, (3) (52) - P-type mineralization region, +41 (5
3) -N type diffusion region, (5) -resistance element, +81-P
type impurity region, ()l (54)--gate electrode, (8
1, - capacitance forming electrode, 1101 (111Q2+031Q
41 (15-911 wiring/port 6071--power supply wiring. Sanyo City Machinery Co., Ltd.)

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device having a delay circuit,
A semiconductor integrated circuit characterized in that a large number of timing adjustment elements including capacitive elements and resistive elements are arranged in a wiring region or a power supply line region, and the timing is adjusted by connecting or disconnecting the timing adjustment elements as appropriate. Device.