JP2013201336A - Semiconductor nonvolatile storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem occurring in a MIS memory transistor which includes resistance means electrically connected with a source region for improving injection efficiency of electric charge that writing reliability is improved but reading margin in an initial state is reduced.SOLUTION: In a MIS memory transistor including resistance means electrically connected with a source region, the resistance means includes variable means for making a value of resistance in data writing be lower than that in data reading.

Description

  The present invention relates to a semiconductor nonvolatile memory device, and more particularly to a structure of a semiconductor nonvolatile memory device including a MIS type memory transistor that changes a threshold voltage by accumulating charges in a charge accumulation layer typified by a MONOS structure.

  An MIS type memory transistor typified by a MONOS structure has a memory insulating film and a memory gate electrode on a channel region sandwiched between a source region and a drain region that are provided apart from an element region defined by an element isolation film. In this structure, the information is stored using a difference between a threshold voltage when charges are accumulated in the memory insulating film and a threshold voltage when charges are not accumulated.

A structure and a writing method of a typical MIS type memory transistor will be described with reference to the drawings.
First, the structure of the MIS type memory transistor will be described. FIG. 11 is a cross-sectional view showing the structure of the MIS type memory transistor, where 101 is a semiconductor substrate, 102 is an element isolation film, and 103 is an element region. Reference numeral 104 denotes a channel region, 105 denotes a memory insulating film, and 106 denotes a memory gate electrode. Reference numeral 107 denotes a source region, 108 denotes a drain region, 109 denotes an interlayer insulating film, 110 denotes a contact hole, 111 denotes a metal wiring, and 120 denotes a depletion layer. Note that the depletion layer 120 schematically shows the spread state by a dotted line in the figure.

  In the MIS type memory transistor shown in FIG. 11, a source region 107 and a drain region 108 are provided apart from each other in an element region 103 defined by an element isolation film 102 provided on a semiconductor substrate 101 with a channel region 104 interposed therebetween. A memory gate gate electrode 106 is provided on the channel region 104 with a memory insulating film 105 interposed therebetween.

  For example, when the MIS type memory transistor is a memory transistor having a MONOS structure, the memory insulating film 105 includes a first insulating film that is a tunnel oxide film, a charge storage layer that is formed of the insulating film, and a second insulating film that is a top oxide film. The threshold value of the memory transistor is controlled by accumulating charges in the charge accumulation layer.

  Further, a metal wiring 111 is provided in connection with the memory gate electrode 106, the source region 107, and the drain region 108 through a contact hole 110 provided in the interlayer insulating film 109.

Next, a method for writing data in the MIS type memory transistor shown in FIG. 11 will be described.
In writing data in the MIS type memory transistor shown in FIG. 11, the gate write voltage VG and the drain write voltage VD are applied to the memory gate electrode 106 and the drain region 108 through the metal wiring 111, respectively, and the memory insulating film 105 is charged. By injecting. The threshold voltage is changed by injecting charges into the memory insulating film 105. No voltage is applied to the source region 107 and the semiconductor substrate 101, and both are at the ground potential.

  The spread state of the depletion layer 120 indicated by a dotted line is different between the vicinity of the source region 107 and the vicinity of the drain region 108. In the vicinity of the source region 107, the spread is small because there is no potential difference between the source region 107 and the semiconductor substrate 101, and in the vicinity of the drain region 108, the spread is caused by a potential difference between the drain region 108 and the semiconductor substrate 101. large.

  In the conventional data writing method described above, it is necessary to increase the surface concentration of the semiconductor substrate 101 in order to increase the efficiency of charge injection into the charge storage layer. However, when the surface concentration is increased, the threshold voltage of the MIS type memory transistor increases, and there is a problem that a MIS type memory transistor that has not been written at the time of reading is erroneously recognized as being written.

  In particular, when the power supply voltage used for reading is low (for example, the power supply voltage is 1.5 V), the problem of erroneously recognizing that data has been written is remarkable. Further, in order to increase the threshold voltage of the MIS type memory transistor after writing, it is necessary to increase the writing voltage. However, it is difficult to increase the writing voltage due to restrictions on the drain junction breakdown voltage of the MIS type memory transistor. It was.

  Further, in the vicinity of the source region 107, the electric field along the channel region 104 in the vicinity of the source region 107 is small, so that charge injection from the channel region 104 in the vicinity of the source region 107 into the memory insulating film 105 does not occur. Therefore, charge is injected into the memory insulating film 105 only from the channel region 104 in the vicinity of the drain region 108, so that the charge injection efficiency is poor and it is difficult to increase the threshold voltage of the MIS type memory transistor.

  Therefore, as a method of enabling sufficient charge injection into the memory insulating film 105 and increasing the threshold voltage of the MIS type memory transistor at the time of writing data, it is connected to the source region of the MIS type memory transistor and is the same as the memory gate electrode. The inventor has proposed a structure that is provided with resistance means that is formed simultaneously with the formation of the memory gate electrode.

  In the technology, when a write voltage is applied to the memory gate electrode and the drain region to inject charges into the memory insulating film, the resistance means connected to the source region causes a potential difference between the source region and the semiconductor substrate. The charge is injected into the memory insulating film from the vicinity of the source region by this potential difference (see, for example, Patent Document 1).

The prior art disclosed in Patent Document 1 will be described with reference to FIG.
FIG. 12 is a diagram in which the technique described in Patent Document 1 is rewritten to facilitate comparison with FIG. 11 and is a cross-sectional view showing the structure of a MIS type memory transistor that is a semiconductor nonvolatile memory device. Resistor means 115 connected to the source region of the MIS type memory transistor is provided. In addition, the same number is provided to the same structure already demonstrated.

  The resistance means 115 is made of the same material as the memory gate electrode and is formed simultaneously with the formation of the memory gate electrode. In the following description, a semiconductor nonvolatile memory device having an N channel MIS type memory transistor and a P type resistance means 115 will be described as an example.

First, the structure will be described with reference to FIG.
The resistance means 115 connected to the source region 107 of the MIS type memory transistor is made of polycrystalline silicon having a conductivity type of P type, and is provided on the element isolation film 102 and a contact hole 110 in which one terminal is provided in the interlayer insulating film 109. The metal region 112 is connected to the source region 107 through the via. Although not shown, the other terminal is connected to a write voltage generation source or a power supply voltage generation source.

Next, a data writing method will be described.
In the prior art shown in Patent Document 1 shown in FIG. 12, when data is written, for example, a write gate voltage VG of 9 V is applied to the N-type memory gate electrode 106. At the same time, a write drain voltage VD of 9 V is applied to the drain region 108 having the N conductivity type.
At this time, the P type semiconductor substrate 101 and the source region 107 are at ground potential.

  Current flowing from the drain region 108 into the source region 107 is limited by the resistance means 115 electrically connected to the source region 107. As a result, the potential of the source region 107 becomes higher than that of the semiconductor substrate 101. That is, the source region 107 and the semiconductor substrate 101 are in a potential relationship that is reverse-biased.

  Therefore, since the electric field in the direction along the channel region 104 near the source region 107 during data writing is strengthened, the spread of the depletion layer 121 near the source region 107 increases, impact ionization occurs near the source region 107, and the channel Charge injection from the region 104 to the memory insulating film 105 occurs (note that the area near the source region 107 is larger than the depletion layer 120 shown in FIG. 11).

  That is, in the prior art disclosed in Patent Document 1, in addition to the charge injection from the channel region 104 near the drain region 108 to the memory insulating film 105, the impact ionization near the source region 107 causes the channel region near the source region 107. Charge accumulation from the memory insulating film 105 also occurs from 104. Therefore, the efficiency of charge injection into the memory insulating film 105 is increased as compared with the conventional technique in which the resistance means 115 connected to the source region 107 is not connected.

Japanese Patent No. 3993007 (page 3-4, FIG. 1)

  In the prior art disclosed in Patent Document 1, in order to increase the efficiency of charge injection into the memory insulating film 105, the resistance means 115 electrically connected to the source region 107 is provided. Because of the connection, a predetermined resistance value is always added to the source region 107 regardless of the initial state before data is written and the situation such as when data is written or read.

The semiconductor nonvolatile memory device shown in the prior art disclosed in Patent Document 1 is a so-called gate bias type in which a threshold voltage is controlled by applying a voltage to a memory gate electrode. Therefore, in an initial state where data is not written, a current flows between the source region and the drain region when a voltage equal to or higher than the threshold voltage of the MIS type memory transistor is applied to the memory gate electrode. When this current flows, the MIS type memory transistor can be recognized as an initial state.
Therefore, the initial state is reliably recognized when the current flowing between the source region and the drain region is large. For this reason, it is preferable that the ON resistance of the MIS type memory transistor in the initial state is low.

However, after writing, the threshold voltage of the MIS memory transistor becomes high, and no current flows between the source region and the drain region when a voltage lower than the threshold voltage is applied to the memory gate electrode. Since this current does not flow, the MIS type memory transistor can be recognized as a writing state.
Therefore, the smaller the current flowing between the source region and the drain region, the more reliably the writing state is recognized. For this reason, it is advantageous that the ON resistance of the MIS type memory transistor is higher.

The fact that the MIS type memory transistor is in the initial state can be known by the fact that a current flows between the source region and the drain region. Therefore, the larger the current, that is, the lower the ON resistance, the more stable the read operation.
That is, in the prior art disclosed in Patent Document 1, although the data writing reliability is improved, since the ON resistance is high, the reading operation in the initial state is not stable and the reading margin is reduced.

  The semiconductor nonvolatile memory device of the present invention is to solve such a problem. An object of the present invention is to provide a semiconductor nonvolatile memory device that achieves both improvement in read margin and improvement in write reliability.

  In order to achieve the above object, the semiconductor nonvolatile memory device of the present invention employs the following structure.

A semiconductor substrate has a source region and a drain region, and a channel region between the source region and the drain region, and has a gate electrode through a memory insulating film that accumulates charges on the channel region, and is electrically connected to the source region. Resistance means to
When data writing is performed in which charge voltage is applied to the gate electrode and the drain region to inject charges into the memory insulating film, the resistance means generates a potential difference between the source region and the semiconductor substrate, and the source region is generated by the potential difference. In a semiconductor nonvolatile memory device that accumulates electric charge in the memory insulating film even from the vicinity,
The resistance means has a variable means for making the resistance value lower when data is written than when reading data.

With such a configuration, it is possible to improve both the data read margin and the write reliability.

The resistance means comprises a plurality of resistance elements,
The variable means is characterized in that the resistance value is changed by separating the resistance elements from each other.

  By adopting such a configuration, a resistance means having a high resistance value can be realized.

The resistance means comprises a plurality of resistance elements,
The variable means is characterized in that the resistance value is changed by connecting the resistance elements to each other.

  By adopting such a configuration, it is possible to realize a resistance means having a low resistance value.

  The resistance value when data is written is the same as the resistance value when data is never written.

  With such a configuration, reliability at the time of data writing can be improved.

  The resistance value when data is written is lower than the resistance value when data is never written.

With such a configuration, a data read margin can be improved.

According to the present invention, it is possible to reduce the ON resistance of the MIS type memory transistor in the initial state and simultaneously increase the ON resistance after writing. In other words, it is possible to provide a semiconductor nonvolatile memory device that achieves both improved read margin and improved write reliability. Therefore, it is possible to realize a semiconductor nonvolatile memory device that is more reliable than the prior art.

It is a circuit diagram explaining the outline | summary of the semiconductor non-volatile memory device of this invention. It is a top view explaining the state of the resistance means of Example 1. 3 is a circuit diagram illustrating details of an electrical connection state of the semiconductor nonvolatile memory device according to the first embodiment. FIG. 1 is a plan view showing a first embodiment of Example 1. FIG. 1 is a cross-sectional view showing a first embodiment of Example 1. FIG. 6 is a plan view showing a second embodiment of Example 1. FIG. It is sectional drawing which shows 2nd Embodiment of Example 1. FIG. It is a top view explaining the state of the resistance means of Example 2. 6 is a plan view showing an embodiment of Example 2. FIG. 6 is a cross-sectional view showing an embodiment of Example 2. FIG. It is sectional drawing which shows the structure of a typical MIS type | mold memory transistor. It is sectional drawing explaining the prior art shown in patent document 1. FIG.

The semiconductor nonvolatile memory device of the present invention has a MIS type memory transistor having a resistance means electrically connected to the source region, and the resistance means has a variable means for changing the resistance value of the resistance means. Is a feature.
Due to the variable means, the resistance value of the resistance means is lower when data is written than when data is read.

First, the outline of the semiconductor nonvolatile memory device will be described with reference to FIG. Next, Example 1 will be described with reference to FIGS. Next, Example 2 will be described with reference to FIGS.
The first embodiment shows a case where the entire resistance value is varied by separating the elements constituting the resistance value of the resistance means by the variable means of the resistance means. There are two embodiments depending on how they are separated, and each will be described.
The second embodiment shows a case where the entire resistance value is varied by connecting elements constituting the resistance value of the resistance means by the variable means of the resistance means.

[Overview: Fig. 1]
First, the outline of the semiconductor nonvolatile memory device of the present invention will be described with reference to FIG.
FIG. 1 is a circuit diagram of a semiconductor nonvolatile memory device, and schematically shows a configuration that is not necessary for explanation. This circuit diagram shows a memory cell structure including a MIS type memory transistor, a control transistor, and a resistance means, and shows a typical connection state in the circuit.
In this circuit diagram, the resistance means has variable means for changing the resistance value according to the charge accumulation state (before writing or after writing) of the memory insulating film.

In FIG. 1, 13 is a MONOS memory transistor which is a MIS type memory transistor, and 14 is a control transistor. Reference numeral 15 denotes resistance means. 150 a and 150 b are terminals of the resistance means 15.

The MONOS memory transistor 13 is an N-type (so-called N-channel type) memory transistor. In FIG. 1, it is simply expressed as MONOS.
The control transistor 14 is a P-type (so-called P-channel type) MIS transistor whose drain region is connected to the drain region of the MONOS memory transistor 13. In FIG. 1, it is written as P-MOS.

The resistance means 15 is composed of a plurality of load resistors and metal wiring connected thereto, as will be described in detail later. The variable means for adjusting the resistance value is provided. One terminal 150b of the resistor means 15 is connected to the source region of the MONOS memory transistor 13, and the other terminal 150a is connected to a write voltage (Vpp) generation source. .
Provide.

  By providing the resistance means 15 in connection with the source region of the MONOS memory transistor 13, when writing data in which a write voltage is applied to the gate electrode and the drain region to inject charges into the memory insulating film, A potential difference is generated between the semiconductor substrate and the depletion layer near the source region spreads. By increasing the spread of the depletion layer, impact ionization in the vicinity of the source region becomes prominent, and charges can be injected into the charge storage layer of the MONOS memory transistor 13 not only from the drain region but also from the source region. .

  A so-called gate bias type MIS memory translator that controls a threshold voltage by applying a voltage to a memory gate electrode is a source region and a drain region without applying a voltage to the memory gate electrode in an initial state (before writing). It is a normally ON state in which current flows during Therefore, it is preferable that the ON resistance of the MONOS memory transistor 13 is low.

  However, after writing, in a state where no voltage is applied to the memory gate electrode, a normally OFF state in which no current flows between the source region and the drain region is obtained. Therefore, it is advantageous that the ON resistance of the MONOS memory transistor 13 is higher.

  The resistance means 15 changes the resistance value of the MONOS memory transistor 13 with respect to the charge accumulation state (before or after writing) by the variable means. The resistance value has a predetermined value before data is written (such as after manufacturing the semiconductor device). Then, data is written into the MONOS memory transistor 13, and then the resistance value of the resistance means 15 is increased by the variable means.

  As a result, the amount of current flowing between the source region and the drain region of the MONOS memory transistor 13 is changed, so that the ON resistance of the MONOS memory transistor 13 is substantially changed. The resistance value can be lowered.

[Explanation of structure in which resistance value is varied by separating resistor 1: FIGS. 1, 2 to 5]
As a first embodiment of the first embodiment, a variable means for changing the resistance value by separating a resistance element constituting the resistance means will be described.
In the description, in particular, the MIS type memory transistor that is an N-type (so-called N-channel type) MONOS memory and the control transistor that is a P-type (so-called P-channel type) MOS transistor. A description will be given by taking as an example a configuration including a transistor and a plurality of resistance elements provided in parallel and separated from each other and resistance means that varies the resistance value by cutting a metal wiring individually connected.

[Conceptual Explanation of First Embodiment of Example 1: FIGS. 1 and 2]
First, the concept of the first embodiment will be described with reference to FIG. 1 and mainly using FIG.
FIG. 2 is a plan view schematically showing a state in which the resistance elements constituting the resistance means 15 are separated. In FIG. 2, reference numerals 15a and 15b denote resistance elements. Reference numerals 11a, 11b, and 11c are metal wirings. In this example, the metal wiring 11a becomes a variable means. Reference symbol A is a portion for cutting the metal wiring.

  As shown in FIG. 2, the resistance elements 15a and 15b are resistance elements formed from, for example, a polycrystalline silicon film. Both are arranged in parallel, and the metal wirings 11a and 11b are connected to one terminal, and these are connected to the terminal 150a, or the end itself of extending the metal wiring is the terminal 150a. The other terminal is connected to the metal wiring 11c and is connected to the terminal 150b, or similarly, the end itself of the metal wiring is the terminal 150b. For example, aluminum can be used for the metal wirings 11a to 11c.

The “initial state” shown in FIG. 2 refers to a state immediately after manufacturing the semiconductor nonvolatile memory device or a state before writing data to the MONOS memory transistor 13.
“Immediately after starting writing” refers to a state immediately after starting to write data to the MONOS memory transistor 13.
“After writing” means a state after data is written to the MONOS memory transistor 13, and “when reading” means a state when data is read from the MONOS memory transistor 13.

  As shown in FIG. 2, in the “initial state”, the resistance elements 15a and 15b are connected in parallel, and the resistance value as the resistance means is a parallel combined resistance of these two resistance elements. The resistance value at this time is R0.

  In the state “immediately after the start of writing”, the states of the resistance elements 15a and 15b do not change. When the resistance value immediately after the start of writing is Rw, Rw is equal to the initial resistance value R0 (Rw = R0).

In “after reading” after data is written or “when reading” in which data is read, the resistance element 15a is cut off at the portion A by cutting the metal wiring 11a, so that only the resistance element 15b is obtained.
When the resistance value “after writing” or “when reading” is Re, the resistance value Re is a resistance value R0 in the initial state or a resistance value larger than the resistance value Rw immediately after the start of data writing equal to the resistance value R0 in the initial state. (Re> R0, Re> Rw).

When cutting the metal wiring 11a, there are a case where it is electrically cut by energization and a case where it is physically cut. In the former, the resistance value of the resistance means 15 is varied using a voltage when data is written to the MONOS memory transistor 13. For the latter, for example, a laser cutter that is a wiring cutting device using a laser beam can be used.
In the above-described example, the metal wiring 11a is the variable means, but of course, the metal wiring 11b may be cut. In this case, the metal wiring 11b is the variable means.

[Detailed Description of First Embodiment of Example 1: FIGS. 2, 3 to 5]
Next, details of the first embodiment of Example 1 will be described with reference to FIGS. 2 and 3 to 5.

The feature of the first embodiment of Example 1 is that the resistance value of the resistance means 15 is varied using the voltage when data is written to the MONOS memory transistor 13.

  FIG. 3 is a circuit diagram for explaining the first embodiment (note that FIG. 3 is also used in the second embodiment). FIG. 4 is a plan view simulating the configuration of an actual semiconductor nonvolatile memory device in the region surrounded by a broken line in FIG. FIG. 5 is a cross-sectional view showing a cross section located at the breaking line AA ′ shown in FIG. 4.

  3 to 5, the reference numeral 1 denotes a semiconductor substrate, 2 denotes an element isolation film, and 3 denotes an element region defined by the element isolation film. Reference numeral 5 denotes a memory insulating film, 6 denotes a memory gate electrode, 7 denotes a source region, and 8 denotes a drain region. Reference numeral 9 denotes an interlayer insulating film, and reference numeral 10 denotes a contact hole provided in the interlayer insulating film. Reference numerals 151, 152, and 153 denote resistance elements. Reference numerals 11, 111a, 111b, 111c, and 111d denote metal wirings. In particular, 111a, 111b, and 111c denote metal wirings that are individually connected to resistance elements as resistance means, and 111d denotes a common metal wiring that is connected to all resistance elements. Show. Reference numerals 12a, 12b, and 12c denote narrow portions provided in the metal wirings 111a, 111b, and 111c, respectively. In addition, the same number is provided to the same structure already demonstrated.

  The MONOS memory transistor 13, which is an N-type MIS memory transistor shown in FIG. 3, is defined by an element isolation film 2 on the surface of a P-type semiconductor substrate 1 as shown in FIGS. 4 and 5. Provided in the element region 3. The element isolation film 2 is a silicon oxide film formed by a LOCOS (Local-Oxidation-Silicon) method, which is a general element isolation method, and has a film thickness of, for example, 400 nm.

In the element region 3, a source region 7 and a drain region 8 made of an N-type impurity are provided apart from each other, and a memory insulating film 5 and a memory gate electrode 6 are stacked in this separated region.
Although not shown, the memory insulating film 5 is a first insulating film that is a silicon oxide film that functions as a tunnel oxide film, a charge storage layer that is a silicon nitride film, and a second silicon oxide film that functions as a top oxide film. The insulating film is laminated. The film thickness is, for example, about 2 nm for the first insulating film, 10 nm for the charge storage layer, and about 3 nm for the second insulating film.

  The memory gate electrode 6 is an N-type polycrystalline silicon film, and is electrically conductive on a polycrystalline silicon film formed by a known chemical vapor deposition method (hereinafter referred to as CVD; Chemical-Vapor-Deposition method). It is formed by selectively adding an N-type impurity. The film thickness is, for example, 350 nm.

  Further, an interlayer insulating film 9 is provided on the surface. The interlayer insulating film 9 is a silicon oxide film formed by a known CVD method, for example. Furthermore, metal wirings 11 and 111 a to 111 d for applying a voltage are provided through contact holes 10 provided in a predetermined region of the interlayer insulating film 9. In particular, the metal wiring 111 d is a metal wiring that connects one side to the source region 7 of the MONOS memory transistor 13, and the other is connected in common to a plurality of resistance elements constituting the resistance means 15. The metal wirings 11, 111a to 111d are made of, for example, an aluminum material formed by a known sputtering method.

  As shown in FIGS. 3 to 5, the resistance means 15 is provided with three resistance elements 151, 152, and 153 spaced apart in parallel on the element isolation film 2. The resistance elements 151, 152 and 153 are polycrystalline silicon films having a P-type conductivity, and are formed by selectively adding an impurity having a P-type conductivity to a polycrystalline silicon film formed by a known CVD method. . The film thickness is, for example, 350 nm, and can be formed in the same process as the formation of the polycrystalline silicon film constituting the memory gate electrode 6.

The three resistance elements 151, 152, and 153 that are spaced apart in parallel are connected at one end to the common metal wiring 111 d through the contact hole 10, and the common metal wiring 111 d is the source of the MONOS memory transistor 13. Connect to region 7. Since the three resistance elements 151, 152, and 153 are connected in parallel, the resistance value of the resistance means 15 itself becomes a parallel combined resistance of the three resistance elements, so that the MONOS memory transistor at the time of data writing is reduced. The ON resistance of 13 can be lowered.

  Furthermore, the metal wirings 111a, 111b, and 111c are individually connected through the contact holes 10 to the ends of the three resistance elements 151, 152, and 153 on the side opposite to the connection with the common metal wiring 111d. ing.

  The metal wirings 111a, 111b, and 111c that are individually connected to the resistance elements 151, 152, and 153 are made of any metal wiring so that the metal wirings 111a, 111b, and 111c can be disconnected by a voltage applied when writing data to the MONOS memory transistor 13. Narrow width portions 12a, 12b, and 12c each having a locally thinned portion are provided.

  In the example shown in FIG. 4, the narrow width portions 12a, 12b, and 12c are configured to have shapes in which the line width gradually decreases in a part of the metal wirings 111a, 111b, and 111c, respectively.

  By having the narrow width portions 12a, 12b, and 12c, when data is applied to the MONOS memory transistor 13 when a voltage is applied through the metal wirings 111a, 111b, and 111c, the current is concentrated, so that the current is concentrated. The narrow part that has become is melted. If it is determined in advance which narrow portion is to be blown according to the applied voltage, and the line width of the narrow portion is set accordingly, it is possible to blow any narrow portion 12a, 12b, 12c. it can. That is, any one of the metal wirings 111a, 111b, and 111c can be cut.

  The resistance element connected to the melted metal wiring cannot function as a resistance means because a voltage cannot be applied after data writing. Accordingly, since the resistance of the entire resistance means 15 is increased, the ON resistance of the MONOS memory transistor at the time of data reading is higher than that in the initial state.

  For example, in view of the change in the resistance value of the resistance means 15 before and after data writing, the resistance value for one resistance element 151 may be varied. In that case, a voltage is applied to the resistance means 15 at the time of data writing to such an extent that only the narrow portion 12a of the metal wiring 111a connected to the resistance element 151 is fused.

  Until the narrow width portion 12a is completely melted, the resistance value of the resistance means 15 is a resistance value in a structure in which the three resistance elements 151, 152, and 153 are spaced apart in parallel. However, since the resistance element 151 does not function as a resistance after the narrow width portion 12a is melted, the resistance value of the resistance means 15 is a resistance value in a structure in which two resistance elements 152 and 153 are spaced apart in parallel. This is higher than the resistance value at the time of data writing.

  Since the metal wiring is made of an aluminum material, the resistance value is very low compared to a resistance element made of a polycrystalline silicon film. Therefore, since the resistance element 151 functions as a resistance until the narrow width portion 12a of the metal wiring 111a is completely blown out, the resistance value of the resistance means can be substantially maintained at the initial value.

That is, the resistance means 15 has set the resistance value in the “initial state” shown in FIG. 2 to R0 when data has never been written, that is, after data writing is started, that is, “immediately after the start of writing” shown in FIG. When the resistance value is Rw and the resistance value at the time of data reading, that is, “at the time of reading (after writing)” shown in FIG. 2 is compared with Re, from the start of data writing until the narrow width portion 12a is blown, The relationship between the resistance values is Rw = R0. However, when the data writing is completed, the narrow width portion 12a is blown and the resistance element 151 does not function as a resistance. Or larger immediately after data writing. That is, the relationship between the resistance values including when reading data is Re> R0 and Re> Rw.

[Explanation of Second Embodiment of Example 1: FIGS. 2, 3, 6, and 7]
Next, details of the second embodiment of the first embodiment will be described with reference to FIGS. 2, 3, 6, and 7.
A feature of the second embodiment of the first embodiment is that after writing data into the MONOS memory transistor 13, an arbitrary metal wiring is cut using a cutting means, and the resistance value of the resistance means 15 is varied.

  The circuit diagram of FIG. 3 described in the first embodiment is the same in the second embodiment, and will be described with reference to this. FIG. 6 is a plan view simulating the configuration of an actual semiconductor nonvolatile memory device in the region surrounded by the broken line in FIG. FIG. 7 is a view showing a cross section located at the breaking line BB ′ shown in FIG. 6.

  In FIG. 6, 12d, 12e, and 12f are cutting portions provided corresponding to the metal wirings 111a, 111b, and 111c, respectively. In FIGS. 6 and 7, reference numeral 16 denotes a passivation film, and 17 denotes an opening provided in the passivation film 16. In addition, the same number is provided to the same structure already demonstrated.

  Similar to the first embodiment, as shown in FIGS. 6 and 7, the three resistance elements 151, 152, and 153 constituting the resistance means 15 are provided on the element isolation film 2 so as to be spaced apart in parallel. Cutting portions 12d, 12e, and 12f are provided in the metal wirings 111a, 111b, and 111c connected to the resistance elements 151, 152, and 153, respectively. These cut portions are shown as an example of a shape in which the line width of the metal wiring is reduced.

  Openings 17 are provided in the passivation films 16 corresponding to the cut portions 12d, 12e, and 12f provided in the metal wirings 111a, 111b, and 111c, respectively. That is, the passivation film as a protective film is opened and the cut portion is exposed in a planar manner. The passivation film 16 is a silicon nitride film formed by a known CVD method.

  In the first embodiment, the narrow portions 12a, 12b, and 12c provided in the metal wirings 111a, 111b, and 111c, respectively, are melted by the voltage applied when data is written. That is, the fusing is performed at the time of data writing, but in the second embodiment, the cutting portions 12d, 12e, and 12f are arbitrarily cut after the data writing.

  Since the opening 17 is provided in the passivation film 16, the cut portions 12d, 12e, and 12f exposed in a plane are irradiated with, for example, a laser beam and melted. These can be implemented by using a laser cutter or the like.

In the example shown in FIG. 6, the cutting portion shows an example in which the line width is narrower than that of the metal wiring. Unlike the first embodiment, the cutting portion is not melted by energization. There is no particular limitation on the line width. When a laser cutter is used, the metal wirings 111a, 111b, and 111c can be easily cut. For this reason, it is not necessary to reduce the line width like the cut portions 12d, 12e, and 12f. However, if the shape of the cut portion is different from that of other portions, it is also a mark of the laser beam irradiation position. Therefore, it can be said that the example of FIG. 6 is one of desirable shapes.

  The cutting parts 12d, 12e, and 12f can be melted by an automatic control system incorporating a movable stage on which a semiconductor nonvolatile memory device is mounted. At that time, since the location (coordinates) of the cutting portion can also be found optically using reflection of light or the like, when using a laser cutter using such a system, the cutting portions 12d, 12e, and 12f It can be said that reducing the line width is a preferable shape because the position can be easily read optically.

  Since the metal wirings 111a, 111b, and 111c are sufficiently resistant to the voltage at the time of data writing, unlike the first embodiment, the resistance value of the resistance means 15 after data writing is the same as the “initial state”. This is the resistance value of the combined resistance of the resistance elements 151, 152, and 153.

  After writing data to the MONOS memory transistor 13 and before reading data, by irradiating a laser beam from an arbitrary opening 17 formed in the passivation film 16, for example, the cut portion 12f of the metal wiring 111c is cut. Since the resistance element 153 connected to the cut metal wiring 111c does not function as the resistance means 15, the resistance value of the resistance means 15 becomes the parallel combined resistance value of the two resistance elements 151 and 152, and the resistance value at the time of data writing Get higher.

  That is, the resistance means 15 has set the resistance value in the “initial state” shown in FIG. 2 to R0 when data has never been written, that is, after data writing is started, that is, “immediately after the start of writing” shown in FIG. When the resistance value is Rw and the resistance value at the time of data reading, that is, “at the time of reading (after writing)” shown in FIG. 2 is compared with Re, The relationship between the resistance values is Rw = R0. However, when the data writing is completed, the cutting unit 12f is cut and the resistance element 153 does not function as a resistor. It becomes larger than immediately after writing data. That is, the relationship between the resistance values including when reading data is Re> R0 and Re> Rw.

  The first embodiment and the second embodiment of Example 1 have been described above. In the description, the narrow width portions 12a, 12b, and 12c and the cut portions 12d, 12e, and 12f have been described as examples in which the line width is narrower than that of the metal wirings 111a, 111b, and 111c. The film thickness may be reduced. In this case, only the film thickness may be reduced without changing the line width.

  Moreover, although the wiring resistance formed from the polycrystalline silicon film is shown as the resistance element, it is of course not limited to this. Of course, a diffusion wiring provided by selectively introducing and activating impurities in a semiconductor substrate in an arbitrary region surrounded by the element isolation film may be used.

[Description of structure in which resistance value is variable by connecting resistor: FIGS. 1, 8 to 10]
As Example 2, variable means for changing the entire resistance value by connecting the resistance values of the resistance means will be described.

  The feature of the second embodiment is that the variable means of the resistance means uses a diffused resistor as a resistance element, and a plurality of spaced apart resistors are arranged in parallel, and adjacent diffused resistors are electrically connected if necessary (of course, It can also be separated) to change its resistance value.

First, the concept of the second embodiment will be described with reference to FIG. 1 and mainly using FIG.
FIG. 8 is a plan view schematically showing how the resistance elements constituting the resistance means 15 are electrically connected. In FIG. 8, 15c is a resistance element. Reference numerals 15d and 15e denote electrically floating resistance elements. 11d is a metal wiring. 11e and 11f are metal electrodes for connecting the resistance elements 15d and 15e to the resistance element 15c.

  The resistance elements 15c, 15d, and 15e are constituted by diffusion resistors provided at arbitrary locations on the semiconductor substrate. Each of them is arranged in parallel with a predetermined interval. These resistance elements are of a conductivity type opposite to that of the semiconductor substrate. The metal wiring 11d is connected to one terminal of the resistance element 15c, and these are the terminals 150a. The other terminal is connected to a metal wiring 11c to form a terminal 150b. For example, aluminum can be used for the metal wirings 11d and 11c.

  Metal electrodes 11e and 11f are provided between the resistive element 15c and the resistive element 15d, which are diffused resistors, and above the resistive element 15d and the resistive element 15e, respectively. In the example shown in FIG. 8, these two metal electrodes are provided so as to slightly overlap the short side of the long side of the diffused resistor located on both sides in plan view.

  The metal electrodes 11e and 11f are provided, for example, via an element isolation film between resistance elements which are diffusion resistors provided apart from each other. The signal line ss1 is provided for the metal electrode 11e, and the signal line is provided for the metal electrode 11f. Each of ss2 is connected.

  Signals S1 and S2 from a control circuit (not shown) are applied to the metal electrodes 11e and 11f via the signal lines ss1 and ss2, respectively. The signals S1 and S2 are signal levels having a potential sufficient to invert the semiconductor substrate. Thereby, by applying a voltage to the metal electrodes 11e and 11f as necessary, the conductivity type of the semiconductor substrate surface between the spaced resistance elements 15c, 15d and 15e is reversed to form an inversion layer. Is electrically connected or disconnected. In this way, the resistance value of the resistance means 15 is varied.

  First, the “initial state” is a state in which no voltage is applied to the metal electrodes 11e and 11f, and the resistance value of the resistance means 15 is determined by only the resistance value of the resistance element 15c connected to the metal wirings 11c and 11d. Is done. The resistance value at this time is R0.

  When data is written to the MONOS memory transistor 13, signals S1 and S2 having predetermined signal levels are applied to the metal electrodes 11e and 11f through the signal lines ss1 and ss2. Here, “when writing” is a state corresponding to “immediately after starting writing” described in the first embodiment. This is the state immediately after starting to write data to the MONOS memory transistor 13.

  An electric field is generated below the metal electrodes 11e and 11f by the applied signals S1 and S2, and a region between the resistor element 15c and the resistor element 15d and a region between the resistor element 15d and the resistor element 15e are The inversion layer is formed by inverting the conductivity type on the surface of the semiconductor substrate. Adjacent resistor elements are connected by this inversion layer.

  The example of FIG. 8 (example of “when writing”) shows an example in which all three resistance elements 15c, 15d, and 15e are electrically connected. This increases the resistance width without changing the resistance length. As a result, the resistance value of the resistance means 15 decreases. Therefore, when the resistance value of the resistance means at the time of “data writing” is Rw, Rw is smaller than that in the “initial state” (Rw <R0).

  At the time of “reading” data from the MONOS memory transistor 13, when the signals S1 and S2 are not applied to the metal electrodes 11e and 11f by the signal lines ss1 and ss2 (state 1), only the signal S2 is applied via the metal electrode 11f. There is a case (state 2).

  When the signals S1 and S2 are not applied to either of the metal electrodes 11e and 11f (state 1), if the resistance value of the resistance means 15 at the time of “reading” data is Re, the resistance value of the resistance means 15 is the resistance element. Only the resistance value 15c is equal to the resistance value R0 in the “initial state”, and is larger than the resistance value Rw in the “data writing” state (Re = R0, Re> Rw).

  On the other hand, when the signal S2 is applied to the metal electrode 11f (state 2), the resistance value of the resistance means 15 is a resistance width including the resistance element 15c, the inversion layer, and the resistance element 15d. The resistance value Re is larger than the resistance value Rw at the time of “writing” data, but smaller than the resistance value R0 in the “initial state” (Re <R0, Re> Rw).

[Description of Structure of Embodiment 2: FIGS. 8, 9, and 10]
Hereinafter, the structure of the semiconductor nonvolatile memory device according to the second embodiment will be described in detail mainly with reference to FIGS.
FIG. 9 is a plan view illustrating the configuration of the main part of an actual semiconductor nonvolatile memory device. FIG. 10 is a view showing a cross section located at the breaking line CC ′ shown in FIG. 9.

9 and 10, the reference numeral 18 denotes a well region. Reference numerals 154, 155, and 156 denote resistance elements constituting the resistance means, and correspond to the resistance elements 15c, 15d, and 15e shown in FIG.
111e, 111f, 111g, and 111h are metal wirings. The metal wirings 111e and 111f correspond to the terminals 150b and 150a shown in FIG. Similarly, the metal wirings 111g and 111h correspond to the signal lines ss1 and ss2, respectively.
111i and 111j are metal electrodes, which correspond to the metal electrodes 11e and 11f shown in FIG. 8, respectively.
Reference numerals 130a and 130b denote inversion regions between the resistance means. This is a region where the inversion layer shown in FIG. 8 is formed.

  As shown in FIGS. 9 and 10, the three resistance elements 154, 155, and 156 constituting the resistance means 15 electrically activate impurities in the region surrounded by the element isolation film 2 on the surface of the well region 18. Diffusion resistance provided. For example, the well region 18 is an N-type well provided in the semiconductor substrate 1 having a P-type conductivity, and the conductivity type of impurities constituting the resistance elements 154, 155, and 156 which are diffused resistors is P-type. is there.

  The three resistance elements 154, 155, and 156 are provided to be spaced apart in parallel in a plan view, and metal wirings 111e and 111f are connected to end portions of the resistance element 154 through contact holes 10 provided in the interlayer insulating film 9. ing. In particular, the metal wiring 111 e is connected to the source region 7 of the MONOS memory transistor 13 through the contact hole 10.

  The resistive element 154 and the resistive element 155, and the resistive element 155 and the resistive element 156 are provided with the metal electrode 111i and the metal electrode 111j in the regions that are separated from each other in plan, and the lengths of the resistive elements that are adjacent to each other in plan view. A voltage (signals S 1 and S 2) can be applied from above to a region where the resistive elements are spaced apart from each other so as to slightly overlap the short side portion. Since the inversion layer shown in FIG. 8 is formed inside the semiconductor substrate in this region, these portions are used as the inversion regions 130a and 130b.

In the example described above, the signals S1 and S2 are examples of signal levels having a potential sufficient to invert the semiconductor substrate. However, the signals S1 and S2 are not limited to the voltage level.
The signals S1 and S2 may be at a voltage level that forms a weak inversion layer that weakly inverts the conductivity type of the semiconductor substrate surface between the resistor elements 15c, 15d, and 15e that are separated from each other.

By doing so, a resistance value can be added not only in the resistance length direction but also in the resistance width direction by the weak inversion layer between the resistance elements 15c, 15d, and 15e.
As described above, the selection of whether the inversion layer or the weak inversion layer connects the resistance elements 15c, 15d, and 15e can be arbitrarily determined according to the desired resistance value.

  The present invention can control the ON resistance of the MIS type memory transistor at the time of data writing and at the time of data reading, and thus is suitable for a semiconductor nonvolatile memory device that requires high controllability.

DESCRIPTION OF SYMBOLS 1,101 Semiconductor substrate 2,102 Element isolation film 3,103 Element area 104 Channel area 5,105 Memory insulating film 6,106 Memory gate electrode 7,107 Source area 8,108 Drain area 9,109 Interlayer insulating film 10,110 Contact hole 11, 11a, 11b, 11c, 11d, 111, 111a, 111b, 111c, 111d, 111e, 111f, 111g, 111h Metal wiring 111i, 111j Metal electrode 12a, 12b, 12c Narrow part 12d, 12e, 12f Cutting Part 120, 121 depletion layer 130a, 130b inversion region
DESCRIPTION OF SYMBOLS 13 MIS type memory transistor 14 Control transistor 15, 115 Resistive means 15a, 15b, 151, 152, 153 Resistive element 16 Passivation film 17 Opening 18 Well region

Claims (5)

A semiconductor substrate includes a source region and a drain region, and a channel region between the source region and the drain region, and a gate electrode interposed between the channel region and a memory insulating film for accumulating charges, and electrically connected to the source region. Having resistance means to connect to
The resistance means generates a potential difference between the source region and the semiconductor substrate during data writing in which a write voltage is applied to the gate electrode and the drain region to inject charges into the memory insulating film. In the semiconductor nonvolatile memory device that accumulates charges in the memory insulating film even from the vicinity of the source region due to the potential difference,
2. The semiconductor nonvolatile memory device according to claim 1, wherein said resistance means has variable means for making the resistance value lower during data writing than during data reading. The resistance means comprises a plurality of resistance elements,
The semiconductor nonvolatile memory device according to claim 1, wherein the variable unit changes a resistance value by separating the resistance elements. The resistance means comprises a plurality of resistance elements,
The semiconductor nonvolatile memory device according to claim 1, wherein the variable unit changes a resistance value by connecting the resistance elements to each other.   4. The semiconductor nonvolatile memory device according to claim 1, wherein a resistance value at the time of data writing is the same as a resistance value when data has never been written. 5. 4. The semiconductor nonvolatile memory device according to claim 1, wherein a resistance value at the time of data writing is lower than a resistance value when data has never been written. 5.

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