JPS5927530A - Fabrication of semiconductor device - Google Patents
Fabrication of semiconductor deviceInfo
- Publication number
- JPS5927530A JPS5927530A JP13818682A JP13818682A JPS5927530A JP S5927530 A JPS5927530 A JP S5927530A JP 13818682 A JP13818682 A JP 13818682A JP 13818682 A JP13818682 A JP 13818682A JP S5927530 A JPS5927530 A JP S5927530A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- etching
- contact holes
- emitter region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Abstract
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法に係り、特にその小形
化を計るための改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to an improvement for reducing the size of the semiconductor device.
以下、筒周波高出力トランジスタの製造方法を例ニ七っ
て説明する。高周波面出力トランジスタでは、特性のよ
り４周波化、１島効率化を図る一つの方策として、パタ
ーン寸法の微細化を進める必要がある。Hereinafter, a method for manufacturing a cylindrical frequency high-output transistor will be explained using two and seven examples. In high-frequency surface output transistors, it is necessary to advance miniaturization of pattern dimensions as one measure for achieving four-frequency characteristics and one-island efficiency.
ところで、第１図（ａ）〜（ｄ）は従来のトランジスタ
の製造工程の主要段階に二ヒける状態を示すＷ「面図で
ある。まず、ｉ４ｉ １図（ａ）に示す、Ｌうにｎ形半
導体基体（１）の表面に第１の酸化１漢（２］を６００
０Ａ〜７００ＯＡの厚さに形成し、ホトエツチング作業
によってペース領域形成のためＶＣ第１の酸化１模（２
）に開孔（力を形成する。次に第１図（ｂ） ＶＣ示す
ように、開孔（３）からホウ素を拡散またはイオン注入
してｐ形のベース領域（４）を形成した後、ベース領域
（４）の表面上を含めて第１の酸化膜（２）の上ＶＣ第
２のｒ膜化ＩＪ＊ （５］を形成する。次ＶＣ箒１図（
Ｃ）に示すように、ベース領域（４）上の一部ｖｃ４％
ｚの酸化ｖ（５）ＶＣホトエツチング作業によって開孔
（６）を形成し、この開孔（６）を介してヒ＄、を拡散
またはイオン注入してｎ形のエミッタ領域（７）を形成
し、その上面を含め℃全上面に第３の酸化ＩＩＩ ＋８
Ｊを形成する。つづいて、４１図（ｄ）に示すようにベ
ース領域（４）およびエミッタ領域（７）の上にそれぞ
れコンタクトホール（９）および四を形成し。By the way, FIGS. 1(a) to 1(d) are cross-sectional views showing the main stages of the conventional transistor manufacturing process. 600% of the first oxide (2) is applied to the surface of the shaped semiconductor substrate (1).
The VC first oxide 1 pattern (2
) to form an opening (force). Next, as shown in FIG. 1(b) VC, boron is diffused or ion-implanted through the opening (3) to form a p-type base region (4). A VC second R film IJ* (5) is formed on the first oxide film (2) including the surface of the base region (4).
As shown in C), some vc4% on the base area (4)
An opening (6) is formed by VC photoetching operation, and an n-type emitter region (7) is formed by diffusing or ion-implanting H $ through this opening (6). , the third oxide III on the entire upper surface including its upper surface +8
Form J. Subsequently, as shown in FIG. 41(d), contact holes (9) and 4 are formed on the base region (4) and emitter region (7), respectively.
このコンタクトホール（９１、（ＩＩＪをｄし石図示シ
ナい電極を形成する。This contact hole (91, (IIJ) is d to form a thin electrode as shown in the stone diagram.
ところが、この従来の方法では、コンタクトホール（９
１、ｔＩＱを開孔するときに、ベース領域（４）の上と
エミッタ領域（７）の上とは酸化膜質は等しく、膜厚が
異なｐベース領域（４）の上が厚いので、エミックコン
クク上ホール四が先に開孔を完了し、その後ベースコン
タクトホール（９）の開孔を完了するまで数回オーブン
で加熱してレジストを焼き付は体からエツチングを繰シ
返えさなければならない。However, in this conventional method, the contact hole (9
1. When opening a tIQ hole, the quality of the oxide film is the same on the base region (4) and on the emitter region (7), but the film thickness is different on the p base region (4), which is thicker. The upper contact hole (4) must be completed first, and then the resist must be heated several times in the oven and etched from the body until the base contact hole (9) is completed. .
このように、エミッタコンタクトホール１ｌｔＪはすＣ
に開孔しているにも刀１かわらず、ベースコンタクトホ
ール（９）の開孔するまでエツチングｉｆ／（浸される
ので：サイドエッチングを受け、設計値通りのパターン
寸法の実現ができμいばかりでμく、不良の発生につ１
４がっていた。In this way, the emitter contact hole 1ltJ is C
Even though the hole is opened in the base contact hole (9), it is etched until the base contact hole (9) is opened. It's difficult to keep track of defects, and
4 was angry.
この発明は以上のような点に鑑みてなされたもので、第
２の酸化膜と第３の酸化膜との膜質を変化さぜることＶ
Ｃよって、２つのコンタクトホールが実質的に同時に形
成完了させ、精度よ（コンタクトポールを形成し、パタ
ーンの小形化が可能な半導体装置の製造方法を提供−ｒ
ることを目的としている。This invention has been made in view of the above points, and it is possible to change the film quality of the second oxide film and the third oxide film.
C. Therefore, it is possible to complete the formation of two contact holes at substantially the same time, and to provide a method for manufacturing a semiconductor device that can form contact poles with high accuracy and reduce the size of the pattern.
The purpose is to
第２区１（＆）〜（ｃ）はこの発明の一実施例の要部段
階ＶＣおける状態を示す断面図で、第１図の従来例と同
等部分は同一符号で示す。第１区１（ａ）および（ｂ）
の段階と全く同様にしてベース領域（４１を形成し、そ
の後ＶＣ第２の酸化ＩＪｉ （５ａ）を形成する。この
第２の酸化ＩＩＩ Ｃ３ａ）としては後述の第３の酸化
膜（８ａ）より被エツチング速度が１．２〜１．４倍の
１摸質のもの１ＯＶＤ法で３０００〜４０００Ａの厚さ
に形成する。っづい工、第２図（ａ） ＶＣ示すようｔ
て、ベース領域（４）上の一部［４２の酸化１漢（５ａ
）にホトエツチング作業によって開孔（６）を形成し、
この開孔（６）を介してヒ素を拡散またはイオン注入し
てｎ形のエミッタ領域（７］を形成し、その後に熱酸化
によって第３の酸化膜（８ａ）をエミッタ領域（７７（
１）上で２５００〜３００ＯＡの厚さに形成する。この
第３の酸化膜（８ａ）は熱酸化膜であるので、第２の酸
化膜（５ａ）の上ではエミッタ領域（７３の上に比べて
酸化膜成長がはるかＶＣ少ない。仄に第２図（ｂ） Ｖ
Ｃ示すようにベース領域（４）お上びエミッタ領域（７
）の上にホトエツチング作業によってそれぞれコンタク
トポール（９）およびＣ１（Ｊを形成するが、このとき
前述のように第２の酸化膜（社）とｇシ３の酸化膜（８
ａ）とでは膜質がｓ／ｊ Ｄ 、かつ嬉２の酸化膜（５
ａ）上の第３の酸化膜（８ａ）はエミッタ領域（７）の
直上の第３の酸化膜Ｃａｋ）に比してはるかに薄いので
、両コンタクトホール（９１，四は殆んど同時に完成さ
せることができる。その後に、第２図（０）に示すよう
に、金属電極材料を蒸着後、所要のエツチングを施して
ベース電極（Ｉりおよびエミッタ電極囮を形成して半導
体装置を完成する。Section 2 1(&)-(c) is a sectional view showing the main part of an embodiment of the present invention at the stage VC, and parts equivalent to those of the conventional example in FIG. 1 are designated by the same reference numerals. District 1 1(a) and (b)
A base region (41) is formed in exactly the same manner as in the step 2, and then a VC second oxide IJi (5a) is formed.This second oxide III C3a) is formed from the third oxide film (8a) described later. A mock-up with an etching speed of 1.2 to 1.4 times is formed to a thickness of 3000 to 4000 Å using the 1 OVD method. Figure 2 (a) VC as shown.
Then, a part on the base region (4) [42 oxide 1 (5a
) by photoetching to form an opening (6),
Arsenic is diffused or ion-implanted through this opening (6) to form an n-type emitter region (7), and then a third oxide film (8a) is formed in the emitter region (77 (7)) by thermal oxidation.
1) Form to a thickness of 2500 to 300 OA on the top. Since this third oxide film (8a) is a thermal oxide film, the oxide film grows much less VC on the second oxide film (5a) than on the emitter region (73). (b) V
As shown in C, the base region (4) and the emitter region (7)
) are formed on contact poles (9) and C1 (J) by photoetching, but at this time, as mentioned above, the second oxide film and the oxide film (8
In a), the film quality is s/j D and the oxide film is 2 (5
a) Since the upper third oxide film (8a) is much thinner than the third oxide film (Cak) directly above the emitter region (7), both contact holes (91 and 4) are completed almost at the same time. Thereafter, as shown in FIG. 2(0), a metal electrode material is deposited and etched as necessary to form a base electrode (I) and an emitter electrode decoy to complete the semiconductor device. .
上記説明ではｎｐｎ形トランジスタを例にとって説明し
たが、その他の半導体装置の製造にも広く）
この発明は適用できるみ一部に２つのコンタクトホール
を形成される半導体領域が互いに独立であってその上の
絶縁膜の１１さが異る場合にも拡張適用できる。In the above explanation, an npn type transistor was used as an example, but the present invention can be widely applied to the manufacture of other semiconductor devices. The present invention can be extended to cases where the insulating films have different 11 values.
以上詳述したように、この発明になる製造方法では一つ
の半導体基体内の２つの半ノ４体頑域の上にそれぞれ形
成され互いＶＣｌφさの異なる絶縁１１Ｑに同時にエツ
チングを捲してコンタクトポールを形成Ｊ−るに際して
、厚さの大きい方の絶縁膜を厚さの小さい方の絶縁膜よ
りも被エツチング速度より太きく１ｊるようＶｃ暎膜質
選んだので、両コンタクトホールの完成時点のｉを少、
なくすることができ・コンタクトホールが４４度よく形
成され半導体装置の小形化がり能で、ある。As detailed above, in the manufacturing method according to the present invention, contact poles are formed by etching the insulators 11Q, which are formed on two half-four solid regions in one semiconductor substrate and have different VClφ, at the same time. When forming the contact holes, the film quality was selected so that the thicker insulating film was 1J thicker than the smaller insulating film at a higher etching speed. less,
・Contact holes can be formed at 44 degrees, making it possible to miniaturize semiconductor devices.
４１図（ａ）〜（ｄ）は従来のトランジスタの製造工程
の主要段階ＶＣおける状態を示す１む［面図、第２図（
ａ）〜（０）はこの発明の一実施例の要部段階における
状態を示す断面図である。
図に、ひいて、（１１は半導体）に体、（４）はベース
領域、（７）はエミッタ領域、（馳）は第２の酸化膜（
絶Ｉ＠嘆）、（８ａ）は第３の酸化１臭（厚さの小さい
絶縁膜） 、［９１゜叫はコンタクトホールである。
なお１図中同一符号は同一または相当部分を示す。
代理人 葛 野 は − （外１名ン
第１図
第２図Figures 41 (a) to 41 (d) show the state at the main stage VC in the conventional transistor manufacturing process.
a) to (0) are cross-sectional views showing states of essential parts of an embodiment of the present invention. In the figure, (11 is the semiconductor) body, (4) is the base region, (7) is the emitter region, (cross) is the second oxide film (
(8a) is the third oxidation layer (a thin insulating film), and (91°) is a contact hole. Note that the same reference numerals in each figure indicate the same or corresponding parts. The agent, Kuzuno, is - (1 other person, Fig. 1, Fig. 2)
Claims (1)
それぞれ形成され互いに厚さの異なる絶縁膜に同時にエ
ツチングを施して上記各半導体領域に達するコンタクト
ホールを形成する工程を有する半導体装置の製造方法に
おいて、上記悶絶縁１模の膜質を互いに異ならしめ、厚
さの大きい絶縁膜の被エツチング速度が厚さの小さい絶
縁１漢の被エツチング速度より大きくなるように上記膜
質を選ぶことを特徴とする半導体装置の製造方法。 （２）悶絶縁膜の被エツチング速度がそれぞれの上記絶
縁膜の厚さに比例するように膜質を選ぶことを特徴とす
る特ｒ１−請求の範囲第１項記載の半導体装置の製造方
法。[Claims] [11] A step of simultaneously etching insulating films formed on the surfaces of two semiconductor regions in one semiconductor substrate and having different thicknesses to form contact holes reaching each of the semiconductor regions. In the method of manufacturing a semiconductor device, the film quality of the first insulation film is made different from each other, and the film quality is changed so that the etching speed of the thicker insulation film is higher than the etching speed of the thinner insulation film. A method for manufacturing a semiconductor device, characterized by: (2) The method of manufacturing a semiconductor device according to claim 1, characterized in that the film quality is selected so that the etching speed of the insulating film is proportional to the thickness of each of the insulating films.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13818682A JPS5927530A (en) | 1982-08-07 | 1982-08-07 | Fabrication of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13818682A JPS5927530A (en) | 1982-08-07 | 1982-08-07 | Fabrication of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5927530A true JPS5927530A (en) | 1984-02-14 |
| JPH0141014B2 JPH0141014B2 (en) | 1989-09-01 |
Family
ID=15216071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13818682A Granted JPS5927530A (en) | 1982-08-07 | 1982-08-07 | Fabrication of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5927530A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5292684A (en) * | 1992-03-28 | 1994-03-08 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device with improved contact and method of making the same |
-
1982
- 1982-08-07 JP JP13818682A patent/JPS5927530A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5292684A (en) * | 1992-03-28 | 1994-03-08 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device with improved contact and method of making the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0141014B2 (en) | 1989-09-01 |
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