JPH01202855A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form emitter width in a bipolar type transistor finely, and to improve high speed properties by determining emitter width through one-time photoetching process. CONSTITUTION:A first conductivity type base region 6 is shaped along the surface of a semiconductor substrate 1, and a thin insulating film 5 and a first polycrystalline silicon film 8 are laminated and formed successively onto the surface of the semiconductor substrate 1. One part of the first polycrystalline silicon film 8 and the insulating film 5 are removed selectively and an emitter window 9 reaching the base region is bored, a second polycrystalline silicon film 11 is applied onto the whole surface, and an impurity is introduced into the base region 6 through the second polycrystalline silicon film 11 to form a reverse conductivity type emitter region 14. The insulating film 5 and the polycrystalline silicon film 8 respectively function as a gate insulating film and a gate electrode in a MIS type transistor in combination. Accordingly, a bipolar MIS type semiconductor integrated circuit having a bipolar type transistor having excellent high speed properties can be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor integrated circuit having bipolar transistors suitable for high-speed operation.

(Prior art) Semiconductor integrated circuits are broadly divided into bipolar integrated circuits and MIS integrated circuits, each of which has the characteristics of high speed and high integration. Bipolar MIS type semiconductor integrated circuits are being actively developed.

A method of manufacturing such a bipolar MIS type semiconductor integrated circuit was as shown in FIG.

FIGS. 2(a) to 2(e) are cross-sectional views in the order of steps of a conventional method for manufacturing a bipolar MIS type integrated circuit.

As shown in FIG. 2(a), N
0 type subcollector region 22, N type epitaxial layer 23
．． P-type well region 24, field insulating film 25, P-type base region 26, gate insulating film 27, and gate electrode 2
8 in sequence.

As shown in FIG. 2(b), highly concentrated arsenic is ion-implanted using the photoresist film 29 and the gate electrode 28 as masks to form an N1 type drain region 30 and an N4 type emitter region 31.

As shown in FIG. 2(C), after forming an interlayer insulating film 32 on the entire surface, contact windows 33 for making electrical contact with each region are formed.

Thereafter, the bipolar MIS type semiconductor integrated circuit is completed through a normal wiring process.

(Problems to be Solved by the Invention) In the above-described conventional method for manufacturing a bipolar MIS type semiconductor integrated circuit, the contact window 33 is opened after the N0 type emitter region 31 is formed.

Considering mask misalignment in the manufacturing process, the N+ type emitter region 31 must be sufficiently larger than the contact window 33. For example, if the minimum processing size of the contact window 33 is 1 unit and the maximum mask misalignment is 1 unit, The minimum emitter width will be 3-. That is, even if extremely fine minimum processing dimensions were achieved, the emitter width of the bipolar transistor could not be made much smaller, and as a result, there was a drawback that the high speed performance could not be improved very much.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit which eliminates the conventional drawbacks, allows the emitter width to be made fine, allows shallow emitters to be formed, and is excellent in high speed.

(Means for Solving Problem 8) A method for manufacturing a semiconductor integrated circuit according to the present invention includes a step of forming a base region of a first conductivity type along the surface of a semiconductor substrate;
A process of sequentially stacking a thin insulating film and a first polycrystalline silicon film on the surface of a semiconductor substrate, and selectively removing a portion of the first polycrystalline silicon film and the insulating film to form a base region. After opening an emitter window that reaches 100 cm, a second polycrystalline silicon film is deposited on the entire surface, and an impurity is introduced into the base region through the second polycrystalline silicon film to form an emitter region of the opposite conductivity type. The insulating film and the polycrystalline silicon film also serve as the gate insulating film and gate electrode of the MIS type transistor, respectively.

(for production) According to the method for manufacturing a semiconductor integrated circuit of the present invention.

A bipolar MIS type semiconductor integrated circuit having bipolar type transistors with excellent high speed performance can be manufactured.

(Example) An embodiment of the present invention will be described based on FIG.

FIGS. 1(a) to 1(f) are cross-sectional views showing the steps of the method for manufacturing a semiconductor integrated circuit according to the present invention.

In FIG. 1(a), a P-type semiconductor substrate 1 is provided with an N0-type subcollector region 2, an N-type epitaxial layer 3, a P-type well region 4, a field insulating film 5, a P-type base region 6, and a gate insulating film 7. are sequentially formed, and a first polycrystalline silicon film 8 is deposited on the entire surface.

Next, as shown in FIG. 1(b), a portion of the first polycrystalline silicon film 8 and gate insulating film 7 are selectively etched away, and an emitter window 9 and a collector contact window 10 are opened. do.

Next, as shown in FIG. 1(e), a second polycrystalline silicon film 11 is deposited on the entire surface. At this time, even if the surface is etched with hydrofluoric acid or the like so that sufficient electrical contact can be made between the second polycrystalline silicon film 11 and the first polycrystalline silicon film 8 or the P-type base region 6, the gate insulating film 7 is not affected because it is covered with the first polycrystalline silicon film 8.

Next, as shown in FIG. 1(d), parts of the second polycrystalline silicon film 11, first polycrystalline silicon film 8, and gate insulating film 7 are selectively removed, and the emitter window 9 is etched away.
Only the peripheral portion of the collector contact window 10 and the gate electrode 12 are left.

Next, as shown in FIG. 1(e), the photoresist film 1
3 as a mask, high-concentration arsenic is ion-implanted to form an N9 type emitter region 14 and an N3 type collector contact region 1.
5 and N4 type drain regions 16 are formed. At this time, since the N0 type emitter region 14 and the N+ type collector contact region 15 are formed by diffusion from polycrystalline silicon, the depth of diffusion is shallower than that of the N0 type drain region 16.

Next, as shown in FIG. 1(f), the entire surface is interlayered.

After forming the edge film 17, a contact window 18 to each region is formed.
Drill a hole.

Thereafter, the bipolar MIS type semiconductor integrated circuit is completed through a normal wiring process.

In this semiconductor integrated circuit manufacturing method, the width of the emitter window 9 is determined by the processing accuracy of the first polycrystalline silicon film 8, and there is no need to take into account misalignment with the contact window. Can be made as small as the minimum processing size. Furthermore, since the impurity is diffused into the emitter region through polycrystalline silicon, the diffusion depth can be made shallow, and as a result, a bipolar transistor with excellent high speed performance can be obtained.

In the embodiment shown in FIG. 1, for convenience of explanation, an NPN type is used as the bipolar transistor and an N-channel type is used as the MIS transistor, but the same effect can be obtained by using the PNP type and P-channel type, respectively. can be obtained, and can also be applied to so-called complementary MIS integrated circuits.

(Effects of the Invention) According to the present invention, since the emitter width of a bipolar transistor is determined by a single photoetching process, the emitter width can be made finer, and a shallow emitter can be formed, resulting in faster processing speed. Able to manufacture excellent semiconductor integrated circuits.

Its practical effects are extremely large.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a process sectional view of a conventional method for manufacturing a semiconductor integrated circuit. 1...P type semiconductor substrate, 2...N0 type subcollector region, 3...N type epitaxial layer, 4...P
type well region, 5... field insulating film, 6...
P-type base region, 7... Gate insulating film, 8... First polycrystalline silicon film, 9... Emitter window, 10...
...Collector contact window, 11... Second polycrystalline silicon film, 12... Gate electrode, 13... Photoresist film, 14... N0 type emitter region, 15.
...N+ type collector contact region, 16...N4
Type drain region, 17... Interlayer insulating film, 18... Contact window. Figure 1Figure 1

Claims (2)

[Claims] (1) A step of forming a base region of the first conductivity type along the surface of the semiconductor substrate, and a step of sequentially laminating and forming a thin insulating film and a first polycrystalline silicon film on the surface of the semiconductor substrate. and selectively removing a portion of the first polycrystalline silicon film and the insulating film to open an emitter window that reaches the base region, and then depositing a second polycrystalline silicon film over the entire surface. and introducing an impurity into the base region through the second polycrystalline silicon film to form an emitter region of an opposite conductivity type. (2) The insulating film and polycrystalline silicon film are each MIS
2. The method of manufacturing a semiconductor integrated circuit according to claim 1, further comprising serving as a gate insulating film and a gate electrode of a type transistor.