JPS5923516A - Placement of reference figure for superposed location - Google Patents

Abstract

PURPOSE:To enable reduction in thickness of the resist film on reference figures and to facilitte signal detection from the figures by a method wherein superposition reference figures are formed at a position higher than the active layer surface of a semiconductor device. CONSTITUTION:Source and drain diffusion regions 3 are provided in the surface layer part of a semiconductor substrate 1, and a gate electrode 4 consisted of polycrystalline Si is formed therebetween through a gate insulating film. Next, field oxide films 2 for isolation are formed on both sides of the region 3, and thick field oxide films 10 continuously extended thereform to form plateaus are further provided on both sides of the oxide films 2. Thereafter, a protructed mark 6 made of polycrystalline Si and a heavy metal mark 8 made of W, etc. are put on the film 10, and a PSG film 5 as an interlayer insulating film is coated all over the surface including those marks, the film 5 being formed at its part with a recessed mark 7. Subsequently, a positive type electron beam resist film 9 for forming contact holes is provided all over the surface. At this time, the thickness of the film 9 is so selected that it has a normal thickness of ca. 1mum and the thickness on the thick oxide films 10 becomes ca. 0.2mum, thereby facilitating detection of figures.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for setting an overlay reference figure used when overlapping transferred figures using a figure transfer method such as an electron beam direct writing method or a reduction projection exposure method, and particularly relates to The present invention relates to a method for installing a reference figure so that the reference figure can be detected easily and with high precision.

Conventional overlay reference figures are generally formed during the manufacturing process of semiconductor devices, and as shown in FIG. It was often installed on a flat surface. However, in the manufacturing process of semiconductor devices, various conductive and insulating layers are often deposited on the surface of the substrate 10, and the reference figure 6.7°8 is often left in a depression surrounded by a high step. Ta. On the other hand, since the photosensitive or electron beam sensitive resist 9 applied for pattern transfer is applied by rotation, the resist surface after coating is relatively flat, and the four parts of the reference figures 6, 7.8, etc."2-II! 4 The thickness tends to be very thick. In this state, when the position of the base 1 figure 6°7.8 is detected, the detection signal is very weak, making it difficult to detect the position with high precision.

Therefore, the object of the present invention is to overcome the drawbacks mentioned above and to solve the problems mentioned above. The object of the present invention is to constantly achieve high detection accuracy of the reference figure in the manufacturing process of the body device.

In order to achieve the above object, the present invention reduces the resist film thickness on the overlay reference figure by forming the overlay reference figure at a higher position than the surface of the active layer of the semiconductor element. This makes it easy to detect signals from the superimposed reference figures mentioned above.

The present invention will be explained in detail below using examples. FIG. 2 shows an example of a seed plateau formed on a semiconductor substrate. The first example is a thick field + 14f2 dielectric film"2 based on 1 (
t+[) with the same figure is shown in 21st; 1(a). In this example, prior to the normal R, 10S element manufacturing process, a field l'+P oxide film 1o of 1μI11 is placed on the part where the reference mark is to be formed, and the field oxide film l
.

A convex 7-ri 6 or the field oxide film 1 formed by processing a POI'si with a film thickness of 0.5 lr m on top.
Q in o, concave mark 7 with a hole of 5μm dJj
Or 0.2μ deposited on the field oxide film lo.
Heavy metal mark 8 formed by processing m-film tungsden film
I set (4).Continued 1 and above 1Self marks (5, 7, 8 are superimposed and used as a reference figure.The MO8 element was formed by superimposing the rough shapes.I in Fig. 2) This shows a typical process of M O formed on a semiconductor substrate 1''2.
The UPS G film 5 is used as an interlayer insulating film on the SIA element.
．． A positive electron beam resist PMM was deposited with a thickness of 6 μm, and a positive electron beam resist PMM was applied to transfer the pattern for forming contact holes.
1 μIn of A9 was applied. In this case, on the normal device region, a J)mu・l M A film 9 with a thickness of about 1μIll is formed, but on the reference figure, this film thickness is 0.2μm8.
degree. Next, an electron beam is irradiated onto the reference figures 6, 7.8, and the 0°L position is detected by capturing the reflected electrons from above the reference figures 6, 7.8. Next, the pattern for contact pole formation is shown in the reference figure 6 above.
Place it based on the 7°8 position. In this case, the appearance of reflected electrons was 10 to 25 times that of the conventional method, and the S/N ratio of the detection signal was dramatically improved, and the overlay accuracy was improved.

As a second embodiment, an example in which a reference figure is provided on a high Si plateau is shown in FIG. 2(b). In this example, prior to the manufacturing process of a normal MO8 element, a region for forming a reference figure is left,
A region where an element or a circuit including an element is to be formed is etched by approximately 1 μm 11, and reference figures 6, 7, .
8 was formed.

FIG. 2(b) shows an example of the same process as in Example 1. Also in this figure, the overlay accuracy was improved due to the same effect as described in Example 1.

As a third embodiment, a Si similar to that shown in the second embodiment is used.
An example is shown in which a plateau is formed using a different method and a reference figure is provided on it. That is, prior to the normal MO8 element manufacturing process -
After forming an S to 2 film of 0.1 μm11 on a CSI substrate and subsequently depositing a polycrystalline Si film of 1 μIll, 1. The same steps as in Example 2 are performed. In FIG. 2(C), Example 1,
An example of the same process as 2 is shown.

Also in this figure, the stacking accuracy was improved with the same effect as described in Example 1.2.

As is clear from the above description, according to the present invention, since the superimposition position reference pattern is located at a higher position than the active layer surface of the semiconductor substrate, the thickness of the resist film spin-coated onto the semiconductor substrate is very much 719 mm above the reference pattern. Therefore, the detection sensitivity is extremely high. Normally, when processing a semiconductor substrate, a resist is often applied with a thickness of 1.5 to 3 times the height of the step on the semiconductor substrate. In this case, the resist film thickness on the platen can be kept to 115 to 1/1 degrees of the resist film on the normal part, and the S/N ratio is more than 3 times that of the conventional method, which is extremely high. Accurate detection becomes possible.

[Brief explanation of drawings]

Claims (1)

[Claims] A method for installing an overlay position reference figure, comprising forming the overlay position reference figure at a higher position than the surface of an active layer of a semiconductor element.