TW594448B - Overlay mark and method for making the same - Google Patents

Abstract

A method for making the overlay mask is described. A material layer is formed on a substrate. Patterning the material layer for forming an outer mark. A first film is formed on the material layer, and performing a planarizing process to remove a portion of the first film. A second film is formed on the material layer covering the first film, wherein the stress of the second film is different from the stress of the first film. Removing the second film on the outer mark, and then forming an inner mark inside the outer mark. Since the second film on the outer mark is removed, the non-uniformity of the second film causing overlay mark measurement error can be avoided.

Description

594448 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a structure of a superimposed mark (0ver lay Mark) and a method for forming the same, and particularly to a method that can avoid the use of superimposed marks in a semiconductor process. Structure of superimposed marks where alignment measurement errors occur during alignment of marks and methods for forming the same. [Prior technology] The factors that usually determine the success or failure of a photolithography process for a wafer. In addition to the control of the critical dimension (Criticai Dimension), another important factor is the alignment accuracy (A1 ignment). Accuracy). Therefore, the measurement of alignment accuracy, that is, the measurement of overlap error, is an important part of the semiconductor process, and the overlap mark is a tool used to measure the overlap error. It is used to judge lithography. Is the photoresist layer pattern patterned in the manufacturing process accurately aligned with the previous film layer on the wafer? Generally, the superimposed mark is designed at the corner of the peripheral edge of the wafer on the wafer to measure the photoresist layer patterned on the photolithography process. The mounting plate = whether there is a precise alignment between the previous film layers on the mouth. quasi. The first image of "wood" Japanese yen is a top view of a person who is familiar in the process of metal interconnects; as shown in Figs. 2A to 2C, it is a cross section of No. 1 1-1. Schematic diagram. Please refer to Figure 1 and Figure 2A. In the process of interconnecting, interconnecting, the first step is to form a dielectric layer 102 on the substrate 100 to a patterned dielectric layer 102, so that A contact window is formed at a specific position (see below), and at the same time, a groove plan (Dian Wei, 104 is used as an external mark (〇Uter Mark) is formed at the place where the superimposed mark is scheduled to be formed.

11531twf.ptd Page 6 594448 V. Description of the invention (2) After that, the metal interconnection process is continued, that is, a metal tungsten layer is formed on the structure formed above, and is filled into the opening of the contact window and the trench 1 04. However, because the width of the trench 104 is wide enough, the metal tungsten will not completely fill the trench 104, and the contact window opening and the metal tungsten layer outside the trench 104 are then removed by chemical mechanical polishing to form a second The metallic iron layer 106 formed in the trench 104 in FIG. . Next, referring to FIG. 2B, after the contact window opening is formed, another metal layer 108 will continue to be deposited on the dielectric layer 102 and the metal tungsten layer 106, and the metal layer 108 will be subsequently defined as a wire. However, because the stress of the metal layer 108 is relatively large, if the stress direction is 1 1 0, the formed metal layer 108 may call for uneven thickness at the trench 104. In other words, the thicknesses of the metal layers 108 on the two sidewalls of the trench 104 are not equal. Please refer to FIG. 1 and FIG. 2C to form a patterned photoresist layer (not shown) on the metal layer 108. This photoresist layer is subsequently used as an etching of the patterned metal layer 108. The mask, in particular, the photoresist pattern 112 formed on the inner periphery of the outer mark by the photoresist layer serves as an inner mark. After that, the step of measuring the superimposed mark is performed, where the dotted line 1 1 4 in Figure 2C is the two corners of the metal layer 1 0 8 above the outer mark 1 0 4 (where the front points are). The center point signal 'same dotted line 1 1 6 is marked by the center point signals at the two edges of the internal mark 1 1 2 (where the arrows point). With the signal 1 1 4 of the external mark 1 0 4 and the signal 1 1 6 of the internal mark 1 12, it can be determined whether the internal mark is accurately aligned with the external mark, and then whether the yellow light process is correct. Quasi-error situation

11531twf.ptd Page 7 594448 V. Explanation of the invention (3), the value of A and A 'in the figure is used to judge whether there is accurate alignment. However, it can be seen in FIG. 2C that the thickness of the metal layer 108 deposited in the trench 104 is not uniform due to the stress. In this way, the signal 1 1 4 generated by the metal layer 108 will also be shifted. In other words, the signal 1 1 4 is not generated where the center of the groove 104 appears. However, at this time, the judgment result of A and A 'is that the internal mark 1 12 is aligned with the external mark 1 04. However, in fact, the yellow light process has already shifted, so if the subsequent definition of this photoresist layer is used, When the metal layer is 108, the contact window opening cannot be accurately aligned with the wire. [Summary of the Invention] Therefore, the object of the present invention is to provide a structure of a superimposed mark and a method for forming the superposed mark, in order to solve the situation that the conventional high-stress film layer can cause the misalignment measurement of the superposed mark. The present invention provides a method for forming a superimposed mark. This method first forms a material layer on a substrate, and patterns the material layer to form an external mark. The external mark can be a trench-type external mark or a raised type. External tag. Next, a first film layer is formed on the material layer, and a flattening step is performed to remove a part of the first film layer. Then, a second film layer is formed on the material layer and covers the first film layer, wherein the stress of the second film layer is different from that of the first film layer, especially the stress of the second film layer is greater than that of the first film layer. Layer of stress. Thereafter, the second film layer above the external mark is removed, or all the second film layers above the external mark and the inner circumference of the outer mark are removed, and an internal mark is formed at the inner circumference of the outer mark after β. The invention proposes a superimposed mark structure, which consists of an external mark

11531twf.ptd Page 8 594448 V. Description of the invention (4) and an internal mark arranged inside the external mark. Among them, the external mark § can be a trench external mark or a convex external mark. Moreover, a first film layer is formed on the side wall of the external mark, and a second film layer is covered on the area other than the external mark, and the stress of the first film layer is different from that of the second film layer. The internal mark is disposed on the second film layer surrounded by the external mark. In another preferred embodiment, except that the second film layer is not covered on the outer mark, the inner wall of the outer mark is not covered with the second film layer, and the inner mark is arranged on the inner wall of the outer mark. Since the present invention removes the second film layer on the external mark, and even removes the second film layer on the inner periphery of the external mark, the external mark will not be affected by the high-stress second film layer at all, but The problem of φ caused by misalignment measurement. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: [Embodiment] The superposition of the present invention The mark and its forming method are to remove the high-stress film layer on the superposed mark to avoid the uneven measurement thickness of the high-stress film layer causing the alignment measurement result of the superposed mark to be shifted. The alignment between the yellow light process and the front film layer of the wafer will be wrong. The following is an example of the structure and method of forming a superimposed mark in a metal interconnect process, but the superimposed mark of the present invention is not limited to use in a metal interconnect process, and in other process steps, Those who have high-stress film layer and adversely affect the alignment measurement of superimposed marks are applicable.

11531twf.ptd Page 9 594448 V. Description of the invention (5) Figure 1 is a schematic top view of a superimposed marker according to one of the preferred embodiments of the present invention; Figures 3 A to 3 G are according to the present invention. A schematic cross-sectional view of a process for forming a superimposed mark in the preferred embodiment is a cross-sectional view from I-I ′ in FIG. 1. Please refer to FIG. 1 and FIG. 3A. In the metal interconnection process, a dielectric layer 102 is first deposited on the substrate 100, and then a lithography process and an etching process are performed to pattern the dielectric layer 1 0 2, and a contact window opening (not shown) is formed in the dielectric layer 102. At the same time, a trench pattern 104 is formed on the wafer where a superimposed mark is to be formed for use as an external mark. In a preferred embodiment, the outer mark of the superimposed mark is composed of a rectangular shape surrounded by four trench patterns 104, and the width of the trench pattern 104 is much larger than the width of the opening of the contact window. Referring to FIG. 3B, a metal layer 105 is deposited on the dielectric layer 102, and the metal layer 105 will fill the contact window openings and trenches 104. However, the contact window openings are far wider It is smaller than the width of the trench 104, so the opening of the contact window will be filled by the metal layer 105, and the trench 104 will not be filled by the metal layer 105. Referring to FIG. 3C, a chemical mechanical polishing process is performed to remove the metal layer 105 outside the opening of the contact window to form a plug structure (not shown). At the same time, the trench 1 0 4 The other metal layers 105 are removed, and the metal layer 106 in the lower trench 104 remains, and the metal layer 106 does not fill the trench 104. Please refer to FIG. 3D. After the contact plug is formed, the dielectric layer is formed. 1 0 2 _ is deposited on another metal layer 108, and the metal layer 108 will be defined as a wire structure connected to the contact plug later. The formed metal layer 108 is marked on the outside.

11531twf.ptd Page 10 594448 V. Description of the invention (6) It will also fill in the trench 104 and cover the metal layer 106, and because the width of the trench 104 is sufficiently large, the metal layer 108 will not cover the trench 104 Fill up. However, because the stress of the metal layer 108 is different from that of the metal layer 106, in particular, the stress of the metal layer 108 is greater than that of the metal layer 106, so the metal layer 108 formed is Will be affected by the stress direction 1 10, and the thickness of the deposit may be uneven. In other words, the thicknesses of the metal layers 108 on the two sidewalls of the trench 104 are not equal. The factors that cause the uneven thickness of the metal layer 108 may be the stress caused by the difference in deposition temperature between the two layers, the stress caused by the structural difference between the two layers, and the bonding between the two layers. The effect of the stress or the stress of φ accumulated by many factors and so on. Please refer to FIG. 3E. In order to eliminate the situation that the measurement of the superimposed mark is offset due to the uneven thickness of the metal layer 108, the present invention removes the metal layer 108 at the superposed mark and removes it. The method is, for example, forming a patterned photoresist layer 200 on the metal layer 108 to expose the overlapping marks on the wafer. The top view is shown in FIG. 4. After that, please refer to FIG. 3F, and use the photoresist layer 2 00 as the # engraving mask to perform an additional step to remove the metal layer 108 not covered by the photoresist layer 2 0 to form a metal layer 108a. The exposed dielectric layer 102 and the metal layer 106 in the trench 104 are exposed. Please refer to FIG. 1 and FIG. 3 G to remove the photoresist layer 200. Then, in order to define the metal layer 108 as a wire, a yellow light process is performed, and a patterned photoresist is formed over the substrate 100. Layer 112a, in which the photoresist layer 112a is located on the wafer where the marks are superimposed 1 1 2 is used as an internal mark

11531twf.ptd Page 11 594448 V. Description of Invention (7) Use. After that, the step of measuring the superimposed mark is performed. In FIG. 3G, the place indicated by the dashed line 202 is the signal of the center point of the metal layer 106 above the outer mark 104 at two corners (where the arrow points). The dotted line 2 0 4 indicates the signal of the center point on the two edges of the internal mark 1 1 2 (where the arrow points). Based on the signal 2 0 2 of the external mark 1 0 4 and the signal 2 0 4 of the internal mark 1 1 2, it can be determined whether the internal mark is accurately aligned with the external mark, and thus whether the yellow light process is aligned. Mistakes. For example, the values of B and B 'in the figure are used to determine whether the alignment is incorrect. It is particularly worth mentioning that, in the above 3E to 3F, the step of removing the metal layer 108 can also remove only the metal layer 108 in the trench 104, and _ retain the outer marker periphery and the inner periphery. The metal layer 10 8 a is shown in FIG. 5. In other words, removing the metal layer 108 with uneven thickness can eliminate the problem of inaccurate alignment measurement caused by uneven film thickness. In the previous step, since the metal layer 1 0 8 that caused the offset measurement in the external mark has been removed, the signal 2 0 2 obtained by the external mark can accurately represent the trench 1 at this time. 0 4 position. In this way, if there is precise alignment between the external mark and the internal mark, it means that the contact window and the subsequent formed wire can be accurately aligned. In the above description, the metal layer outside the contact window opening is removed by using chemical mechanical polishing in the metal interconnection process as an example. Of course, if the etch-back process is used to remove the metal layer outside the contact window opening, ®'s metal interconnect process is also applicable to the present invention, and its diagram is shown in Figure 6. In Figure 6, if the etch-back process is used instead of CMP

11531twf.ptd Page 12 594448 V. Description of the invention (8) (corresponding to the steps in the previous Figure 3 B), only the metal layer 106a located on the side wall of the trench 1 104 will be retained, in other words, the bottom of the trench 104 The metal layer is also removed by the etch-back process, and other process steps are the same as those in the above embodiment. Therefore, in the structure of the superimposed mark in FIG. 6, except that the metal layer 106a is not covered at the bottom of the trench 104, the outer mark 10 (ie, inside the trench 104) and the outer mark 104 are not covered. The inner periphery is not covered with the metal layer 108a. Similarly, in the metal interconnection process using the etch-back process in FIG. 6, the step of removing the metal layer 108 can also remove only the metal layer 108 in the trench 104 and retain the external mark. The metal layer 108a at the periphery and the inner periphery is shown in FIG. In FIG. 7, the external mark 104 (that is, the inside of the ml channel 104) is not covered with the metal layer 108 a, thereby eliminating the problem of inaccurate alignment measurement caused by the uneven thickness of the film layer on the external mark 104. In each of the above embodiments, the external mark is described by taking a trench-type external mark as an example. In fact, the external mark can also be a raised external mark, as shown in Figure 8. In Fig. 8, the dielectric layer 102 has an external mark 1 0 4 a, and the external mark 10 4 a is a raised pattern. In particular, neither the outer marking 1 0 4 a nor the inner circumference of the outer marking 10 4 a is covered with a metal layer 108 a. In addition, the design of the superimposed mark with the raised outer mark may be that the outer mark 1 0 4 a is not covered with the metal layer 1 0 8 a, and the outer mark 104 a is still covered with the outer periphery and the inner periphery. The metal layer 108a is shown in FIG. The above description is based on the superposition mark of the metal interconnection process.

11531twf.ptd Page 13 594448 V. Description of the invention (9), but the superimposed mark and the method of forming the invention are not limited to the metal interconnection process. In other words, the dielectric layer 10 2 may be other materials, such as a conductive material, a silicon material, and the like, and the metal layer 106 or 10 6 a and the metal 10 8 may also be other materials, such as a dielectric material. , Silicon materials, etc. Since the present invention removes the high-stress metal layer on the external mark, and even removes the high-stress metal layer on the inner periphery of the external mark, the external mark will not be affected by the high-stress metal layer at all, and there is alignment. Problems with measurement errors. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The guaranteed reading range of φ shall be determined by the scope of the attached patent application.

11531twf, ptd Page 14 594448 Brief description of the drawing Figure 1 is a schematic top view of a superimposed mark in the metal interconnection process; Figures 2A to 2C are diagrams showing the formation of a stack in the conventional metal interconnection process. Schematic cross-sectional schematic diagrams of composite marking; FIGS. 3A to 3G are schematic cross-sectional schematic diagrams of forming a superimposed mark according to a preferred embodiment of the present invention; FIG. 4 is a schematic diagram above FIG. FIG. Is a cross-sectional view of a superimposed mark according to another preferred embodiment of the present invention, FIG. 6 is a schematic cross-sectional view of a superposed mark according to another preferred embodiment of the present invention; and FIG. 7 is a diagram according to the present invention A schematic cross-sectional view of a superimposed mark according to another preferred embodiment; and FIG. 8 is a schematic cross-sectional view of a superimposed mark according to another preferred embodiment of the present invention; and FIG. 9 is a further preferred embodiment according to the present invention. Schematic cross-section of the superimposed mark. [Illustration of Graphical Symbols] 1 00: substrate 1 02; dielectric layer 104, 10 4a: external marking 106, 108, 108a: metal layer _ 1 1 0: stress direction 1 1 2: internal marking

11531twf.ptd Page 15 594448 Brief description of the drawings 114, 116, 2 0 2, 2 0 4: Signal 112a, 200: Photoresist layer

ill 11531twf.ptd Page 16

Claims (1)

594448 a pattern is carried out in the second removal in the 2. as the method, which will be located on the 3 as the method, wherein the second film layer is formed on the outer marking. 4.Follow the method, where the external mark 5 · Follow the method, where the ini '' is formed on the base of the superimposed standard to form the material layer of the material and a flat material layer film layer of the external external standard application to remove the external standard application Remove the second film of the method and apply for the external layer for a while. Apply for the flat material layer in the surfaceization step. The stress is marked on the surfaceization step. The internal range of the internal mark on the external mark is included. A step of forming an external mark, a method of recording a material layer; forming a layer on top to remove a portion of the first film layer; a second film layer covering the first film layer, which has a different stress from the first film layer; The second film layer; and an inner mark is formed around the second film layer. The step of forming a superimposed mark as described in item 1 above the second film layer further includes removing the second film layer around Xin. The patterned photoresist layer above the square mark forming the superimposed mark and the inner circumference of the outer mark described in item 2 exposes the area corresponding to the inner circumference of the mark; and to remove the area not covered by the photoresist layer The second covering includes: the external marking of the first film layer, the square mark forming the superimposed mark described in item 1 is a trench-type external mark or a raised type (as described in item 1 of the scope of interest). The step of forming a superimposed mark includes performing a chemical mechanical polishing process. 11531twf.ptd Page 17 594448 6. Scope of patent application Perform a one-time etching process. 6. The method for forming a superimposed mark as described in item 1 of the scope of patent application, wherein the stress of the second film layer is greater than that of the first film layer. 7-A structure of a superimposed mark, including: an outer mark; and an inner mark disposed inside the outer mark, wherein a first film layer is formed on a side wall of the outer mark, and The area other than the external mark is covered with a second film layer, and the stress of the first film layer is different from that of the second film layer. In addition, the internal mark is disposed in the second area surrounded by the external mark. Film layer. 8 · The structure of the superimposed mark as described in item 7 of the scope of patent application, except that the outer layer is not covered with the second film layer, the inner circumference of the outer mark is not covered with the first layer. Two layers. 9. The structure of the superimposed mark as described in item 7 of the scope of patent application, wherein the external mark is a trench-type external mark or a raised external mark. 10. The structure of the superimposed mark according to item 7 of the scope of the patent application, wherein the stress of the second film layer is greater than that of the first film layer. 11531twf.ptd Page 18