JPS592281A - バツフアメモリ方式 - Google Patents

バツフアメモリ方式

Info

Publication number
JPS592281A
JPS592281A JP57109322A JP10932282A JPS592281A JP S592281 A JPS592281 A JP S592281A JP 57109322 A JP57109322 A JP 57109322A JP 10932282 A JP10932282 A JP 10932282A JP S592281 A JPS592281 A JP S592281A
Authority
JP
Japan
Prior art keywords
buffer memory
data
memory
processing unit
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57109322A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6214861B2 (enrdf_load_stackoverflow
Inventor
Kenichi Maeda
健一 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57109322A priority Critical patent/JPS592281A/ja
Publication of JPS592281A publication Critical patent/JPS592281A/ja
Publication of JPS6214861B2 publication Critical patent/JPS6214861B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP57109322A 1982-06-25 1982-06-25 バツフアメモリ方式 Granted JPS592281A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57109322A JPS592281A (ja) 1982-06-25 1982-06-25 バツフアメモリ方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57109322A JPS592281A (ja) 1982-06-25 1982-06-25 バツフアメモリ方式

Publications (2)

Publication Number Publication Date
JPS592281A true JPS592281A (ja) 1984-01-07
JPS6214861B2 JPS6214861B2 (enrdf_load_stackoverflow) 1987-04-04

Family

ID=14507284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57109322A Granted JPS592281A (ja) 1982-06-25 1982-06-25 バツフアメモリ方式

Country Status (1)

Country Link
JP (1) JPS592281A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03504992A (ja) * 1989-01-19 1991-10-31 アメリカ合衆国 着色および無着色繊維の連続的な酸化漂白と還元漂白

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6454594U (enrdf_load_stackoverflow) * 1987-10-01 1989-04-04

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5665384A (en) * 1979-10-31 1981-06-03 Nec Corp Information processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5665384A (en) * 1979-10-31 1981-06-03 Nec Corp Information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03504992A (ja) * 1989-01-19 1991-10-31 アメリカ合衆国 着色および無着色繊維の連続的な酸化漂白と還元漂白

Also Published As

Publication number Publication date
JPS6214861B2 (enrdf_load_stackoverflow) 1987-04-04

Similar Documents

Publication Publication Date Title
US4546467A (en) Monitor for transmission line
EP0456491B1 (en) A distributed database management system
EP0261029B1 (en) Cache invalidate protocol for digital data processing system
US5682518A (en) System for updating inactive system memory using dual port memory
US4115851A (en) Memory access control system
US6941433B1 (en) Systems and methods for memory read response latency detection
KR970017010A (ko) 데이터 저장 시스템 및 머신 수행 방법
US5978938A (en) Fault isolation feature for an I/O or system bus
KR100285956B1 (ko) 고속직렬버스에연결된동기식및비동기식장치의제어시스템과제어방법
KR910001522A (ko) 데이타 전송방법과 이 방법을 사용한 데이타 처리 시스템
KR920020316A (ko) 컴퓨터 시스템에서 트랜잭션을 수행하기 위한 쿼드러쳐 버스 프로토콜
US4698754A (en) Error detection of scan-out in a diagnostic circuit of a computer
KR860000594A (ko) 버퍼기억장치용 태그 제어회로
JPS592281A (ja) バツフアメモリ方式
US5771345A (en) Integrated digital processing device and method for examining the operation thereof
KR100249171B1 (ko) 비동기식 데이터 송수신 장치의 에러 검출 방법
CN119473801B (zh) 基于axi协议的总线超时监测方法、装置及系统
US5307488A (en) System interruption apparatus
JPH10307763A (ja) バス監視装置
JP2002132743A (ja) メモリアクセス監視装置、メモリアクセス監視方法およびメモリアクセス監視用プログラムを記録した記録媒体
JPH02294751A (ja) キヤツシユメモリ制御装置
JP2590855B2 (ja) 障害情報管理装置
JP2821326B2 (ja) キャッシュメモリの故障検出装置
JPS59220851A (ja) 履歴情報収集装置
JPH0484233A (ja) プログラム動作状況記録方式