JPS59224158A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS59224158A JPS59224158A JP9910983A JP9910983A JPS59224158A JP S59224158 A JPS59224158 A JP S59224158A JP 9910983 A JP9910983 A JP 9910983A JP 9910983 A JP9910983 A JP 9910983A JP S59224158 A JPS59224158 A JP S59224158A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistor
- integrated circuit
- forming
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 本発＃Ｊは、集積回路装置に関するものである。[Detailed description of the invention] This issue #J relates to an integrated circuit device.
従来、集積側Ｎ装置は、トランジスタ、抵抗、コンデン
サなどの素子を不純物拡散等の素子形成工程でｌｂ成し
、その後配線工程で素子を結線することによシ、回路を
構成していた。一般に抵抗はトランジスタのベース拡散
工程で形成していた。Conventionally, in integrated N devices, circuits have been constructed by forming elements such as transistors, resistors, and capacitors in an element formation process such as impurity diffusion, and then connecting the elements in a wiring process. Generally, resistors are formed in the transistor base diffusion process.
したがって抵抗数が多くなるとチップ面積が太きくなり
ていた。また、注弓埋振幅や゛電流の調整などによる抵
抗値の変更や、不純物のドーズ譬の調整などによる抵抗
形成条件の父！Ｊ！、勿竹う場合、抵抗としての拡般領
域の、７：＠き１足は素子形成工程そのものを変具しな
ければならず、震災後の集積回路装置ができ上るまで４
目当な時間を袈し、ＩＮ時間で変更でさない。また抵抗
が、成工程をすぎたものは抵抗イｌの変更及び抵抗形成
飛付の変タミができない欠点がめった。Therefore, as the number of resistors increases, the chip area becomes larger. In addition, the resistance formation conditions can be changed by changing the resistance value by adjusting the injection amplitude and current, and by adjusting the dose of impurities. J! , of course, the expansion area as a resistor would require modification of the element formation process itself, and it would take 4 hours until the integrated circuit device was completed after the earthquake.
Set the desired time and do not change it at IN time. Moreover, if the resistor has passed through the forming process, it is difficult to change the resistor shape or to change the resistor formation jump.
この発明は、抵抗を配線形７５′（工程後、配縁形成層
上に杷縁欣を形成し、その上に多結晶シリコン抵抗を形
成することによシ、抵抗領域分のテップ面積を小ざくで
さ、また、すべての配線形成工程が利子した後に抵抗を
形成するので抵抗値の変更及び抵抗形成条件の変更が容
易であシ、それにともなう時間の損失が小さくできるＳ
積回路装置を提供するものである。This invention reduces the step area for the resistor region by forming the resistor in a wired type 75' (after the process, forming a lobe edge on the edge forming layer and forming a polycrystalline silicon resistor thereon). In addition, since the resistor is formed after all the wiring forming steps have been completed, it is easy to change the resistance value and the resistance forming conditions, and the time loss associated with this can be reduced.
The present invention provides an integrated circuit device.
以下図面を参照し、本発明をよシ詳細に説明する。第２
図は本発明の一実施例による集積回路装置の断面図で図
において、８は素子形成層、９は素子形成層−Ｉ ＪＶ
７１Ｊ配線層間分離ノ餐、１０は１層配線層、１１は１
層配線層−２１−配線層間分離ノ“１４．１２は２層配
線ｊジ、１３は２層配線％）−抵抗形成ノー間分離層、
１４は抵抗形成層、Ｊ５はチップ保護層である。本実施
例に卦いては図より＋ｇ４らかなように素−Ｆ形成層で
抵抗を形成ぜすに抵抗ｉ１４成１ψ１で抵抗を形成する
ことによｐチップ面積を小さくできる。The present invention will be explained in detail below with reference to the drawings. Second
The figure is a cross-sectional view of an integrated circuit device according to an embodiment of the present invention. In the figure, 8 is an element formation layer, 9 is an element formation layer - I JV
71J wiring layer separation, 10 is 1st wiring layer, 11 is 1st wiring layer
Layer wiring layer-21-wiring layer separation (14.12 is 2nd layer wiring, 13 is 2nd layer wiring%)-resistance formation layer,
14 is a resistance forming layer, and J5 is a chip protection layer. In this embodiment, the p-chip area can be reduced by forming the resistor with the resistor i14 and 1ψ1 instead of forming the resistor with the element -F forming layer, as shown in the figure.
第３図は本発明の他の実施例でイ）る。第３図において
、１６は素子形成ノー、１７け先仔形成ＪＱテで形成し
ている抵抗領域、１８は素子形成層−１７ψ配線層間分
離ｊ曽、１９は１層配線層、２０け１１ｔ’ｊ配線層−
２ノ〜配線層間分離層、２１は２層配線層、２２は２層
配；糊胸−Ｃ１： Ｊ′Ａ：形放層間分煎Ｍ、２３ｄ：
抵抗形成層、２４ ｒｊ：チン・フ保訂１（・マで之・
る。本実前例においては、素子形成層で抵抗を形成し１
、さらに抵抗形成層も形成する。こ）１．け抵抗がトラ
ンジスタと同一形成条件でなければならないものとそう
でないものが、ともに有る始合である。この」ハ合も抵
抗形成層に形成する抵抗領域分だけチップ面積を／ＪＸ
さくできる。FIG. 3 shows another embodiment of the present invention. In FIG. 3, 16 is the resistance region formed by the element formation node, 17 is the resistor region formed by the first layer formation JQ, 18 is the element formation layer-17ψ wiring layer separation j, 19 is the first wiring layer, and 20 is the resistance region formed by 11t'. j wiring layer-
2--wiring layer separation layer, 21 is a two-layer wiring layer, 22 is a two-layer arrangement; Glue chest-C1: J'A: Shape laminar separation M, 23d:
Resistance-forming layer, 24 rj: Chin Fu, revised 1 (・Madeno・
Ru. In this practical example, a resistor is formed in the element formation layer.
, and further forms a resistance forming layer. This) 1. There are some cases in which the resistor must be formed under the same conditions as the transistor, and others in which it is not. In this case, the chip area is reduced by the resistance area formed in the resistance formation layer.
I can write it.
本発明による集積回路装置は従来の集積回路装置と比較
して抵抗形成ノーに形成する抵抗領域分チップ面桓を小
さくでき、さらに抵抗を形成するのは集積回路装置を構
成する最終工程であるため抵抗値の変更及び抵抗形成ノ
ーを変更する場合、抵抗形成層以前の工程にもどる必要
がなく、それら変更にともなう時間の損失がＪ・さい。Compared to conventional integrated circuit devices, the integrated circuit device according to the present invention can reduce the chip surface area by the amount of the resistor area formed before resistor formation, and furthermore, the resistor is formed in the final step of configuring the integrated circuit device. When changing the resistance value and the resistance formation number, there is no need to return to the steps before forming the resistance formation layer, and the time loss associated with these changes is J.
以上説明したとおり、本発明によれは素子及び配線形成
後の工程において多結晶シリコン抵抗を形成することに
より、抵抗形成層に形成する抵抗外だけチップ面積を小
さくでき、捷だ抵抗値の変更及び抵抗形成条件の変更が
容易に行うことができる。As explained above, according to the present invention, by forming a polycrystalline silicon resistor in a process after forming elements and wiring, the chip area can be reduced except for the resistor formed in the resistor formation layer, and the resistance value can be easily changed and Resistor formation conditions can be easily changed.
第１図は７従来の集積回路装置の断面図、第２図、第３
図は本発明の各実施例による集積回路装置の断面図であ
る。
１．８．１６・・・・・・素子形成層、２．１７・・・
・・・素子形成ノーで形成している抵抗領域、３，９．
１８・・・・・・素子形成層−１層配線層間分離層、４
，１０１９ ・・・・・・ １ ノ曽自己線層、 ５
． １１． ２０ ・・・・・・ １ ノψｉ配
＃５層−２層配線層間分離層、６，１２．２１・・・・
・・２層配線層、１３．２２・・・・・・２層配線層−
抵抗形成層間分離層、１４．２３・・・・・・抵抗形成
層、７゜１５．２４・・・・・・チップ保護ｊ曽。
゛・乳・ン°・Figure 1 is a cross-sectional view of seven conventional integrated circuit devices, Figure 2, Figure 3.
The figure is a sectional view of an integrated circuit device according to each embodiment of the present invention. 1.8.16...Element formation layer, 2.17...
. . . Resistance region formed in element formation no. 3, 9.
18...Element formation layer-1 layer wiring interlayer separation layer, 4
,1019... 1 Noso self-line layer, 5
．． 11. 20...1 No.ψi layout #5 layer-2 layer wiring interlayer separation layer, 6,12.21...
...2nd wiring layer, 13.22...2nd wiring layer -
Resistance forming layer separation layer, 14.23...Resistance forming layer, 7°15.24...Chip protection.゛・Breasts・n°・
Claims (1)
に形成し−た記録層で前記値数の半導体素子間を接続し
た集積回路装置において、前記配線層上に多結晶シリコ
ン抵抗を形成したことを特徴とする集積回路装置。In an integrated circuit device in which a plurality of semi-integrated elements are arranged in a semiconductor substrate and the number of semiconductor elements are connected by a recording layer formed on the semiconductor substrate, a polycrystalline silicon resistor is formed on the wiring layer. An integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9910983A JPS59224158A (en) | 1983-06-03 | 1983-06-03 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9910983A JPS59224158A (en) | 1983-06-03 | 1983-06-03 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59224158A true JPS59224158A (en) | 1984-12-17 |
Family
ID=14238654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9910983A Pending JPS59224158A (en) | 1983-06-03 | 1983-06-03 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59224158A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5275963A (en) * | 1990-07-31 | 1994-01-04 | International Business Machines Corporation | Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom |
| EP0598101A1 (en) * | 1992-06-05 | 1994-05-25 | United States Department Of Energy | Process for forming synapses in neural networks and resistor therefor |
-
1983
- 1983-06-03 JP JP9910983A patent/JPS59224158A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5275963A (en) * | 1990-07-31 | 1994-01-04 | International Business Machines Corporation | Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom |
| US5381046A (en) * | 1990-07-31 | 1995-01-10 | International Business Machines Corporation | Stacked conductive resistive polysilicon lands in multilevel semiconductor chips |
| EP0598101A1 (en) * | 1992-06-05 | 1994-05-25 | United States Department Of Energy | Process for forming synapses in neural networks and resistor therefor |
| EP0598101A4 (en) * | 1992-06-05 | 1995-11-15 | Us Energy | Process for forming synapses in neural networks and resistor therefor. |
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