JPH0766944B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a plurality of upper circuit forming areas, each of the plurality of upper circuit forming areas having a plurality of lower basic circuit forming areas, while The present invention relates to a semiconductor integrated circuit device in which each circuit forming region has a functional circuit forming region forming a functional circuit and a plurality of connecting internal terminals derived from the functional circuit.

[Prior art]

Conventionally, a semiconductor integrated circuit device described below with reference to FIG. 3 has been proposed. That is, a plurality of, for example, two upper circuit formation regions A ₁ and
With A ₂ . The upper circuit formation area A ₁ has a plurality of, for example, two lower basic circuit formation areas B ₁₁ and B ₁₂ . The upper circuit formation area A ₂ also has a plurality of, for example, two lower basic circuit formation areas B ₂₁ and B ₂₂ . Further, the lower basic circuit formation regions B ₁₁ , B ₁₂ , B ₂₁ and B ₂₂ are
Each has functional circuit formation regions C ₁₁ , C ₁₂ , C ₂₁ and C ₂₂ which form a functional circuit (not shown). The lower basic circuit formation area B ₁₁ is a functional circuit formation area C.
A plurality of, for example, two connecting internal terminals F ₁₁₁ and F ₁₁₂ derived from ₁₁ are provided. Further, the lower basic circuit formation region B ₁₂ is derived from the functional circuit formation region C ₁₂ . It has two connection internal terminals F ₁₂₁ and F ₁₂₂ corresponding to the connection internal terminals F ₁₁₁ and F ₁₁₂ of the lower basic circuit formation region B ₁₁ . Further, the lower basic circuit forming area B ₂₁ is connected to two connecting internal terminals F ₁₁₁ and F ₁₁₂ corresponding to the connecting internal terminals F ₁₁₁ and F ₁₁₂ of the lower basic circuit forming area B ₁₁ which are derived from the functional circuit forming area C ₂₁ . It has internal terminals F ₂₁₁ and F ₂₁₂ . The lower basic circuit forming region B ₂₂ has a lower basic circuit forming region connecting internal terminals F ₁₁₁ and F ₁₁₂ 2 pieces of connecting the internal terminal F221 and F222, which correspond to the B11. In this case, the lower basic circuit forming areas B ₁₁ , B ₁₂ , B ₂₁ and B ₂₂
The internal terminals F ₁₁₁ , F _121, F _212, and F ₂₂₁ for connection of are the terminals that are connected to each other by automatic wiring after that, and the lower basic circuit formation regions B ₁₁ , B ₁₂ , B _21, and B _22. It should be noted that the connection internal terminals F ₁₁₁ , F ₁₂₁ F ₂₁₁ and F ₂₂₂ are terminals which are connected to each other by automatic wiring after the same. The above is the configuration of the conventionally proposed semiconductor integrated circuit device. The semiconductor integrated circuit device having such a configuration is
Using the automatic wiring device, the internal terminal F ₁₁₁ for connection of the lower basic circuit forming areas B ₁₁ and B ₁₂ of the upper basic circuit forming area A ₁ and
F ₁₂₁ and the lower basic circuit forming area B of the upper circuit forming area A ₂
And ₂₁ and connecting the internal terminals F ₂₁₁ and F ₂₂₂ of B ₂₂ is a wiring L ₁₁ and L ₂₁ in the upper circuit forming regions A ₁ and A _2, and the wiring L _a1 between the upper circuit forming regions A ₁ and A ₂ Are connected to each other, and the connecting internal terminals F ₁₁₂ and F ₁₂₂ of the lower basic circuit forming areas B ₁₁ and B ₁₂ of the upper circuit forming area A _{1 and} the lower basic circuit forming area B _{21 of the} upper basic forming area A ₂ are connected. And internal terminals F ₂₁₁ and F ₂₂₂ for connection of B ₂₂ are connected to the upper circuit formation area A ₁
And the wirings L ₁₂ and L ₂₂ in A ₂ and the upper circuit formation area A ₁
And A ₂ are connected to each other by a wiring L _a2 ,
Used.

[Problems to be Solved by the Invention]

However, in the case of the conventional semiconductor integrated circuit device shown in FIG. 3, the above-mentioned wiring L ₁₁ ,
When L ₁₂ , L ₂₁ , L ₂₂ , L _a1 and L _a2 are formed, first,
In the first stage, wirings L ₁₁ and L ₁₂ and wirings L ₂₁ and L
₂₂ and then wirings L _a1 and L _a2 are formed,
In this case, from the algorithm that can be taken in the automatic wiring device, the wirings L ₁₁ and L ₁₂ are formed at the predetermined side edge positions of the upper circuit formation area A ₁ so as to be extended so that the connection rate is high, and the positions P 11 and When located at P12, the above wiring L
₂₁ and L ₂₂ is the upper circuit forming region A ₁ of the upper circuit forming region A ₂
To the side edge position corresponding to the side edge position of P, extended so as to increase the connection rate, positioned at positions P ₂₂ and P ₂₁ respectively corresponding to positions P ₁₂ and P ₁₁ , and wiring L _a1 and L _It may _happen that _a2 is extended between positions P ₁₁ and P _{22 and} between positions P ₁₂ and P _21, respectively. Therefore, the wiring layers L _a1 and L _a2 described above may be formed to intersect each other as shown in the figure between the upper circuit formation regions A ₁ and A ₂ , and the wiring layers L _a1 and L _a2 may be formed to intersect each other. In this case, there is a drawback that a wiring layer forming region having a large area is required as compared with the case where the wiring layer is formed without crossing. Therefore, the present invention proposes a novel semiconductor integrated circuit device without the above-mentioned drawbacks.

[Means for Solving the Problems]

The semiconductor integrated circuit device according to the present invention has a plurality of upper circuit formation regions, as in the case of the conventional semiconductor integrated circuit device described above with reference to FIG. A plurality of lower basic circuit forming areas, and each of the plurality of lower basic circuit forming areas forms a functional circuit, and a plurality of connection internals derived from the functional circuit. And a terminal. However, in the semiconductor integrated circuit device according to the present invention, in the semiconductor integrated circuit device having such a configuration, each of the plurality of lower basic circuit formation regions has a plurality of unconnected external terminals for connection and the internal connection terminals. It has a wiring layer forming region for forming a wiring connecting the terminal and the external terminal for connection.

[Action / effect]

According to the semiconductor integrated circuit device of the present invention, each of the plurality of lower basic circuit formation regions includes a functional circuit formation region,
Wiring for forming a wiring layer for connecting the plurality of connection external terminals and the plurality of connection internal terminals and the plurality of connection external terminals, in addition to having the plurality of connection internal terminals derived therefrom. It has the same structure as the conventional semiconductor integrated circuit device described above with reference to FIG. 3, except that it has a layer forming region,
Then, subsequently, using the automatic wiring device, in each of the plurality of lower basic circuit forming regions in each of the plurality of upper circuit forming regions, the plurality of connecting internal terminals and the plurality of connecting external terminals are formed in the wiring layer forming region. A plurality of external terminals for connection in a plurality of lower basic circuit formation areas in one upper circuit formation area in the plurality of upper circuit formation areas, and the external terminals for connection, which are respectively connected to each other. Wiring in which a plurality of external terminals for connection in a plurality of lower basic circuit formation regions in another higher circuit formation region in a plurality of higher circuit formation regions extend between one higher circuit formation region and another higher circuit formation region Used by being connected to each other. Therefore, as in the case of the conventional semiconductor integrated circuit device described above with reference to FIG. 3, after that, it is wired by the automatic wiring device and used. However, according to the semiconductor integrated circuit device of the present invention, each of the plurality of lower basic circuit formation regions in each of the plurality of higher circuit formation regions is derived from the plurality of connection external terminals and those and the functional circuit formation region. When a wiring layer forming region for forming wirings for connecting a plurality of internal terminals for connection is formed, and the automatic wiring apparatus is made to carry out the wirings described above, the conventional method described in FIG. 3 is used. As in the case of the semiconductor integrated circuit device of FIG. 3, it is possible to provide an algorithm that does not cross the wiring between the one upper circuit formation region and the other one higher circuit formation region, and therefore, the conventional method described in FIG. The above-mentioned drawbacks of the semiconductor integrated circuit device can be effectively avoided.

First Embodiment Next, a first embodiment of the semiconductor integrated circuit device according to the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor integrated circuit device according to the present invention shown in FIG. 1 has the same configuration as the conventional semiconductor integrated circuit device described above with reference to FIG. 3 except for the following matters. That is, the lower basic circuit formation region B ₁₁ in the upper circuit formation region A ₁ is the functional circuit formation region C ₁₁ and the connecting internal terminals.
In addition to F ₁₁₁ and F ₁₁₂ , it has two unconnected external terminals G ₁₁₁ and G ₁₁₂ corresponding to the internal terminals F ₁₁₁ and F ₁₁₂ for connection formed at the planned side edge positions. , A wiring layer forming region for forming wiring for connecting the connection internal terminals F ₁₁₁ and F ₁₁₂ and the connection external terminals G ₁₁₁ and G ₁₁₂
With H ₁₁ . In addition, the lower basic circuit forming area B ₁₂ in the upper circuit forming area A ₁ includes the functional circuit forming area C ₁₂ and the connecting internal terminal F _121.
In addition to F ₁₂₂ and F ₁₂₂ , it was also formed at the planned side edge position,
Unconnected 2 corresponding to internal terminals F ₁₂₁ and F ₁₂₂ for connection
In addition to having individual external terminals G ₁₂₁ and G ₁₂₂ for connection,
Internal terminals for connection F ₁₂₁ and F ₁₂₂ and external terminal for connection G ₁₂₁ and
It has a wiring layer formation region H ₁₂ for forming a wiring for connecting to G ₁₂₂ . Further, the lower basic circuit forming area B ₂₁ in the upper circuit forming area A ₂ is the functional circuit forming area C ₂₁ and the connecting internal terminal F.
_{In addition to 211} and F ₂₁₂ , it has two unconnected external terminals G ₂₁₁ and G ₂₁₂ corresponding to the internal terminals F ₂₁₁ and F ₂₁₂ for connection formed at the planned side edge position, Wiring layer formation region for forming wiring for connecting the internal terminals F ₂₁₁ and F ₂₁₂ for connection and the external terminals G ₂₁₁ and G ₂₁₂ for connection
Has H ₂₁ . In addition, the lower basic circuit formation region B ₂₂ in the upper circuit formation region A ₂ includes the functional circuit formation region C ₂₂ and the connection internal terminal F _221.
And outside the F ₂₂₂ , it was also formed at the planned side edge position,
Unconnected 2 corresponding to internal terminals F ₂₂₁ and F ₂₂₂ for connection
While having external terminals G ₂₂₁ and G ₂₂₂ for connection to each,
Connection internal terminals F ₂₂₁ and F ₂₂₂ and connection external terminals G ₂₂₁ and
It has a wiring layer formation region H ₂₂ for forming a wiring for connecting to G ₂₂₂ . The above is the configuration of the embodiment of the semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device according to the present invention having such a configuration has the internal terminals F ₁₁₁ and F ₁₂₁ for connection of the lower basic circuit formation regions B ₁₁ and B _{12 in} the upper circuit formation region A ₁ and the upper circuit formation region A ₂ Lower basic circuit formation areas B ₂₁ and B _{22 in}
Connection internal terminals F ₂₁₂ and F ₂₂₁ are connected internal terminals F _{212 in} the wiring layer formation region H ₁₁ of the lower basic circuit formation region B _11.
Wiring L ₁₁₁ extending between ₁₁₁ and external terminal G ₁₁₁ for connection
And a wiring L ₁₂₁ extending between the connection internal terminal F ₁₂₁ and the connection external terminal G _{121 in} the wiring layer formation region H ₁₂ of the lower basic circuit formation region B _{12, and} a wiring of the lower basic circuit formation region B ₂₁ . The wiring L ₂₁₁ extending between the connection internal terminal F 212 and the connection external terminal G ₂₁₁ in the layer formation region H ₂₁ and the connection internal terminal F _{221 in} the wiring layer formation region H ₂₂ of the lower basic circuit formation region B _22. And the wiring L ₂₂₁ extending between the external terminal for connection G ₂₂₁ and the external circuit connecting areas A ₁ and A ₂ and the external terminals for connection G ₁₁₁ , G ₁₂₁ , G ₂₁₁ and G ₂₂₁ are connected and extended. Are connected to each other by the wiring L _a1 that is connected to each other, and the internal terminals F ₁₁₂ and F ₁₂₂ for connection of the lower basic circuit formation areas B ₁₁ and B _{12 in} the upper circuit formation area A ₁ and the upper circuit formation area A ₂ are connected. Internal terminal F ₂₁₁ for connection of lower basic circuit formation areas B ₂₁ and B ₂₂
And F ₂₂₂ , the wiring L ₁₁₂ extending between the connection internal terminal F ₁₁₂ and the connection external terminal G _{112 in} the wiring layer formation area H ₁₁ of the lower basic circuit formation area B ₁₁ , and the lower basic circuit formation area B _11. internal terminal F for connecting the wiring layer formation region H _{12 12}
Wiring L ₁₂₂ extending between ₁₂₂ and external terminal G ₁₂₂ for connection
And a wiring L ₂₁₂ extending between the internal connecting terminal F211 and the external connecting terminal G _{212 in} the wiring layer forming area H ₂₁ of the lower basic circuit forming area B _{21, and} the wiring layer of the lower basic circuit forming area B ₂₂ . The wiring L ₂₂₂ extending between the connection internal terminal F ₂₂₂ and the connection external terminal G ₂₂₂ in the formation area H22 and the connection external terminals G ₁₁₂ , G ₁₂₂ , and G ₂₁₂ between the upper circuit formation areas A ₁ and A _2.
, And G ₂₂₂ , which are connected to each other and extended by a wiring L _a2 that is used. And in this case, the internal terminal F ₁₁₁ for connection to the automatic wiring device
It is possible to recognize the external terminals for connection G _{111 to} G _{222 in addition} to the elements from F ₂₂₂ to F _222. Therefore, from the algorithm that can be adopted in the automatic wiring device, the wirings L _a1 and L _a2 are respectively positioned as described above in FIG. It can be formed by extending between P ₁₁ and P ₂₁ , and between P ₁₂ and P ₂₂ . Therefore, according to the semiconductor integrated circuit device of the present invention, it is possible to effectively avoid the drawbacks described above in the conventional semiconductor integrated circuit device described in FIG.

Second Embodiment Next, another embodiment of the semiconductor integrated circuit device according to the present invention will be described with reference to FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor integrated circuit device according to the present invention shown in FIG. 2 has the same configuration as the semiconductor integrated circuit device according to the present invention described above with reference to FIG. 1 except for the following matters. That is, in the upper circuit formation area A ₁ , the connection external terminals G ₁₁ ′ and G ₁₂ ′ corresponding to the connection external terminals G ₁₁₁ and G ₁₁₂ in the lower basic circuit formation area B ₁₁ and the wiring layer formation area H. A terminal processing region B ₁ ′ having a wiring layer formation region H ₁ ′ corresponding to ₁₁ is provided, and the upper circuit formation region A ₁
, The external terminals for connection corresponding to the external terminals for connection G ₁₁₁ and G ₁₁₂ in the lower basic circuit formation region B ₁₁
A terminal processing area B ₂ ′ having G ₁₁ ′ and G ₁₂ ′ and a wiring layer forming area H ₂ ′ corresponding to the wiring layer forming area H ₁₁ is provided. It is apparent that the configuration of the semiconductor integrated circuit device according to the present invention as described above can provide the operation and effect similar to the case of FIG.

[Brief description of drawings]

FIG. 1 is a systematic connection diagram showing a first embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 2 is a systematic connection diagram showing a second embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 3 is a systematic connection diagram showing a conventional semiconductor integrated circuit device. A _1, A ₂ ...... higher circuit forming region B ₁₁ .about.B ₂₂ ...... lower basic circuit forming region C ₁₁ -C ₂₂ ...... functional circuit forming region F ₁₁₁ to F ₂₂₂ inside for ...... connection terminal G ₁₁₁ ~G ₂₂₂ ...... External terminals for connection H _{11 to} H ₂₂ …… Wiring layer formation area L _a1 , L _a2 , L _{111 to} L ₂₂₂ …… Wiring P _{11 to} P ₂₂ …… Position

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display area H01L 27/04 H01L 27/04 A

Claims (1)

[Claims] 1. A plurality of upper circuit forming areas, each of the plurality of upper circuit forming areas has a plurality of lower basic circuit forming areas, and each of the plurality of lower basic circuit forming areas has a function. In a semiconductor integrated circuit device having a functional circuit forming region forming a circuit and a plurality of connecting internal terminals derived from the functional circuit, each of the plurality of lower basic circuit forming regions is unconnected. A semiconductor integrated circuit device comprising: a plurality of connecting external terminals; and a wiring forming region for forming a wiring connecting the plurality of connecting internal terminals and the plurality of connecting external terminal layers. .