JPS5922396A - Method of producing multiwire circuit board - Google Patents

Method of producing multiwire circuit board

Info

Publication number
JPS5922396A
JPS5922396A JP13259582A JP13259582A JPS5922396A JP S5922396 A JPS5922396 A JP S5922396A JP 13259582 A JP13259582 A JP 13259582A JP 13259582 A JP13259582 A JP 13259582A JP S5922396 A JPS5922396 A JP S5922396A
Authority
JP
Japan
Prior art keywords
wire
layer
insulating
substrate
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13259582A
Other languages
Japanese (ja)
Inventor
山崎 正踐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP13259582A priority Critical patent/JPS5922396A/en
Publication of JPS5922396A publication Critical patent/JPS5922396A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明はマルチワイヤ配線板の製造方法に関し、特にス
ルホールめっき工程中に使用するめっきレジスト層の形
成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multi-wire wiring board, and particularly to a method for forming a plating resist layer used during a through-hole plating process.

近年、ICをはじめとする実装部品の小型化、高集積化
の発展に伴ない、印刷配線板に対しても配線パターンの
高精度化、高密度化などの要求が強くなっている。さら
にニーズの多様化につれて、生産の多品種、少量化傾向
も顕著になってきている。
In recent years, as mounting components such as ICs have become smaller and more highly integrated, there has been a growing demand for higher precision and higher density wiring patterns for printed wiring boards. Furthermore, as needs become more diversified, there is a growing tendency to produce a greater variety of products in smaller quantities.

マルチワイヤ配線板は絶縁被覆ワイヤを、配線基板上の
絶縁性接着剤層上に交差配線することにより信号回路を
形成している。
A multi-wire wiring board forms a signal circuit by cross-wiring insulated wires on an insulating adhesive layer on a wiring board.

従って印刷配線板の製作上必要であった原画、写真など
のアートワークを必要としないばかりか実装の高密度化
を容易にし、多品種少量生産におけるコストパーフォマ
ンスの改善に寄与している。
Therefore, not only does artwork such as original drawings and photographs that are necessary in the production of printed wiring boards become unnecessary, but it also facilitates high-density mounting, contributing to improved cost performance in high-mix, low-volume production.

この株の従来マルチワイヤ配線板の代表的な一例を第1
図および第2図を参照して説明する。第1図(a)の如
く無電解めっき用触媒を含む絶縁基板lの上に必要に応
じて例えば電源層、接地層として使用することができる
ようにバタン化した桐箔j@2を片面又は画商に形成し
、次に第1図([))の如く、絶縁J板lおよび@箔層
2に接して無′tイ解めっき用触媒を含む接着層3を形
成した後、第1図(C)の如く信号回路としての絶縁被
覆ワイヤ4の所望回路パターンを、例えば数値制ail
1式自動布線装置により、接着層3に布線固着させ、さ
らに第1図(d)の如く布線固着した絶縁被覆ワイヤ4
による回路パターンを保護し、かつ固着を確実にするた
めに無電解めっき用触媒を含むプリプレグを積層接涜す
ることにより無は解めっきに対して触媒性を有する絶縁
層(以下触媒性絶縁層と称す)5を形成する。
A typical example of this stock's conventional multi-wire wiring board is shown below.
This will be explained with reference to the figures and FIG. As shown in Fig. 1(a), on an insulating substrate l containing a catalyst for electroless plating, paulownia foil j@2, which has been made into a batten, is coated on one side or so that it can be used as a power supply layer or a ground layer, if necessary. Then, as shown in Fig. 1 ([)], after forming an adhesive layer 3 containing a catalyst for non-plating plating in contact with the insulating J plate 1 and @ foil layer 2, as shown in Fig. 1 A desired circuit pattern of the insulating coated wire 4 as a signal circuit as shown in (C) is created using, for example, a numerical system.
The wires are fixed to the adhesive layer 3 using a type 1 automatic wiring device, and then the insulated wire 4 is fixed to the adhesive layer 3 as shown in FIG. 1(d).
In order to protect the circuit pattern and ensure adhesion, a prepreg containing a catalyst for electroless plating is laminated to form an insulating layer (hereinafter referred to as a catalytic insulating layer) that has catalytic properties against deplating. 5).

さらに外表++iに無電解めっきに対して触媒性を有し
ない非整合マスク層(以下マスク)−と称す)6を形成
した後、第1図(e)の如く所望の位置に絶縁被覆ワイ
ヤおよび銅箔層2を横切るように貫通JL7を穿設し、
絶縁被覆ワイヤ4および@箔層2の少なくとも一部を貫
通孔7の内面に露出させ之後、無電解めっき液に浸漬す
ることにより貫通孔7の壁面に金属導体層8を形成して
スルホールとし、第1図(f)の如くマスク層6を除去
して第2図に示すようなマルチワイヤ配線板を形成°f
るものであった。
Furthermore, after forming a non-conforming mask layer (hereinafter referred to as "mask") 6 which does not have catalytic properties against electroless plating on the outer surface ++i, insulated wires and copper are placed at desired positions as shown in FIG. 1(e). A through hole JL7 is bored across the foil layer 2,
At least a portion of the insulating coated wire 4 and @ foil layer 2 are exposed on the inner surface of the through hole 7, and then a metal conductor layer 8 is formed on the wall surface of the through hole 7 by immersing it in an electroless plating solution to form a through hole, As shown in FIG. 1(f), the mask layer 6 is removed to form a multi-wire wiring board as shown in FIG.
It was something that

このようなマルチワイヤ配線板の従来の製造工程に於け
るめっきレジスト層としてのマスク層6は、めっき終了
後に剥離する事を前提として加工を施し5ていた。
In the conventional manufacturing process of such a multi-wire wiring board, the mask layer 6 as a plating resist layer was processed 5 on the assumption that it would be peeled off after plating was completed.

マスク層6はポリエチレンシートの片面に粘着性の樹脂
層を塗布したもので、基板への貼り合わせは熱圧着と言
う手段に依っていたが、温度55〜70°Cと言う高温
の無電解めっき俗に長時間曝されたり、孔明は時の機械
的なストレス等に依り、時として安定なめっきレジスト
層としての働きが維持出来ず、部分的なマスクのハガレ
や破損の為に、めっき不可部分への、めっき析出が生じ
る事が有った。
The mask layer 6 is made by coating one side of a polyethylene sheet with an adhesive resin layer, and pasting to the substrate was done by thermocompression bonding, but electroless plating at a high temperature of 55 to 70°C was used. In general, due to long-term exposure or mechanical stress, it is sometimes impossible to maintain the function of a stable plating resist layer, and parts of the mask that cannot be plated may be peeled off or damaged. In some cases, plating precipitation occurred.

本発明はこの様な従来の欠点を改良したマルチワイヤ配
線板の製造方法を提供することにある。
The object of the present invention is to provide a method for manufacturing a multi-wire wiring board that overcomes these conventional drawbacks.

本発明によれば絶縁基板上に絶縁被覆ワイヤを布線固着
して回路パタンを形成すると共に、ワイヤの終端部を基
板上に穿設された貫通孔の孔壁上に無電解めっきのスル
ホール導電層を形成して接続されてなるマルチワイヤ配
線板の製造方法において、絶縁被覆ワイヤ布線後のパタ
ーン上に無覗j、イめっきに対して触媒性を有する絶縁
性耐脂層の形成が終了した基板に対して絶縁性樹脂層上
の全域に無電解めっきに対して触媒性を有しない絶縁P
Lインクを塗糊する工程を含む事を1時機としたマルチ
ワイヤ配線板の製造方法が得られる。
According to the present invention, a circuit pattern is formed by wiring and fixing an insulating coated wire on an insulating substrate, and the terminal end of the wire is electrolessly plated on the hole wall of a through hole drilled on the substrate. In the method for manufacturing a multi-wire wiring board formed by forming and connecting layers, the formation of an insulating, fat-resistant layer having catalytic properties against plating is completed on the pattern after wiring the insulating coated wires. Insulating P, which does not have catalytic properties against electroless plating, is applied to the entire area on the insulating resin layer for the substrate.
A method for manufacturing a multi-wire wiring board is obtained, which includes the step of applying L ink and pasting.

以下、本発明を第3図を参照して説明する。The present invention will be explained below with reference to FIG.

第3図は本発明の一実施例を示す断ff(1図である。FIG. 3 is a diagram showing one embodiment of the present invention.

第3図(a)けFjfJ述した従来例の第1図(a)な
い[7第1図(C)と同様にして製造した中間工程の配
線板の状態を示すものである。この配線板の表裏画面に
無1F解めっきに対して触媒性を有するプリプレグの所
望枚数を重ねた構成体の上下両面を十分な剛性を有する
例えばステンレス鋼で作った平面板(図示省略)にて挾
持し、この平面板構成体を加熱、加圧]7て触媒性絶縁
層5を形成する。このM:It媒性杷錬層5の形成の後
に、触媒性絶縁1−5の外側に無電解めっきに対して触
媒性を有しない熱硬化性のインクを塗糊し、これを加熱
等の手段に依り、硬化させる。
FIG. 3(a) shows the state of the wiring board in the intermediate process manufactured in the same manner as in FIG. 1(C) of the conventional example described above. A desired number of sheets of prepreg having catalytic properties against non-1F deplating are stacked on the front and back screens of this wiring board, and the upper and lower surfaces of the structure are made of planar plates (not shown) having sufficient rigidity and made of stainless steel, for example. The planar plate structure is then held and heated and pressurized]7 to form a catalytic insulating layer 5. After the formation of this M:It medium embellishment layer 5, a thermosetting ink that does not have catalytic properties for electroless plating is applied to the outside of the catalytic insulation 1-5, and this is pasted by heating etc. Harden depending on the method.

以上の方法により第3図(b)のごとく、無電解めっき
に対して触媒性を有しない絶縁層(以下、非触媒性絶縁
層と称−′j)9を形成する。
By the above method, as shown in FIG. 3(b), an insulating layer 9 having no catalytic properties for electroless plating (hereinafter referred to as a non-catalytic insulating layer) 9 is formed.

次に第3図(C)のごとく、所望の位置に絶縁被覆ワイ
ヤ4および銅箔層2を横切るように貫通孔7を穿設し、
絶縁被覆ワイヤ4およびf(1+I箭層2の少なくとも
一部を貝i瓜孔7の内壁面に露出させた後無電解めっき
液に浸l貢することにより貫通孔7の内壁面に、第3図
(d)のごとく金属導体層8を形成した。
Next, as shown in FIG. 3(C), a through hole 7 is bored at a desired position so as to cross the insulated wire 4 and the copper foil layer 2,
After exposing at least a part of the insulation coated wires 4 and f(1+I) to the inner wall surface of the shell hole 7, a third layer is formed on the inner wall surface of the through hole 7 by immersing it in an electroless plating solution. A metal conductor layer 8 was formed as shown in Figure (d).

非触媒性絶縁層91i基板内外層と同様に安定、且つ、
強固に形成きれているため、従来のマスク層6の使用時
に見られた破損等によるめっき不可部分へのめっき析出
がないので、めっきレジスト層としての用済み後におい
ても、基材の保護用として製品の一部を構成させても何
ら支障がないばかりか、残留による基板に対する保護体
としての効果は大なるものがある。
The non-catalytic insulating layer 91i is stable like the inner and outer layers of the substrate, and
Because it is firmly formed, there is no plating precipitation on areas that cannot be plated due to damage etc. that was seen when using the conventional mask layer 6, so even after it is used as a plating resist layer, it can be used to protect the base material. Not only does it pose no problem even if it forms part of a product, but the residual material also has a great effect as a protector for the substrate.

以上本発明により次の効果が得られた。As described above, the following effects were obtained by the present invention.

(1)めっき時に従来のめっきレジスト層以上の密Ii
性ヲ、唯持することが出来るため、めっき導体によるブ
リッジの発生や、絶縁不良等の発生が1氏、威出来た。
(1) During plating, the density Ii is higher than that of conventional plating resist layer.
Because it is possible to maintain the properties of the conductor, it has been possible to reduce the occurrence of bridging due to plated conductors and poor insulation.

(ト)従来のようなめっきレジスト層の除去が不要な為
、工数低減及びリードタイム短縮のメリットは言うに及
ばず、除去時に多発していた基板表面の破損を皆無に出
来た。
(g) Since it is not necessary to remove the plating resist layer as in the conventional method, there are not only advantages of reduced man-hours and lead time, but also the damage to the substrate surface that frequently occurs during removal can be completely eliminated.

(iiQ  部品実装時以降の基板の機械的及び耐環境
的安定性が向上する。
(iiQ The mechanical and environmental stability of the board after component mounting is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(f)は従来のマルチワイヤ配置tの製
造工程の断面図、第2図は第1図の斜視図、第3図(,
11〜<d)は本発明のマルチワイヤ配線板の:!A造
工哩の断mj図。 l・・・・・・絶縁基板、2・・・・・・(内層)銅箔
ノー、3・・・・・・接着層、4・・・・・・絶縁被覆
ワイヤ、5・・・・・・触媒性絶縁層、6・・・・・・
マスク層、7・・・・・・貫通孔、8・・・・・・金属
導体層、9・・・・・・非触媒性絶縁層。 ? 壊?図
1(a) to 1(f) are cross-sectional views of the manufacturing process of the conventional multi-wire arrangement t, FIG. 2 is a perspective view of FIG. 1, and FIG.
11~<d) of the multi-wire wiring board of the present invention:! Cross-sectional mj diagram of A construction factory. l...Insulated substrate, 2...(Inner layer) copper foil, 3...Adhesive layer, 4...Insulated wire, 5... ...Catalytic insulating layer, 6...
Mask layer, 7... Through hole, 8... Metal conductor layer, 9... Non-catalytic insulating layer. ? Destruction? figure

Claims (1)

【特許請求の範囲】[Claims] 絶W、基板上に絶縁被覆ワイヤを布線して11路バタン
を形成すると共に、前記ワイヤの終端部を基板上に設け
られた貫通孔の孔壁上に無電解めっきのスルホール導電
層を形成して接続されてなるマルチワイヤ配線板の製造
方法において、絶縁被覆ワイヤ布線後のパターン上に無
電解めっきに対して触媒性を有する絶縁性樹脂層の形成
が終了した基板に対して、前記絶縁性樹脂層上の全域に
無電解めっきに対して触媒性を有しない絶縁性インクを
塗糊する工程を含む事を特徴としたマルチワイヤ配線板
の製造方法。
At the same time, wire an insulated coated wire on the substrate to form an 11-way button, and form an electroless-plated through-hole conductive layer on the hole wall of the through-hole provided on the substrate at the terminal end of the wire. In the method for manufacturing a multi-wire wiring board connected by the following process, the above-mentioned method is applied to a substrate on which an insulating resin layer having catalytic properties for electroless plating has been formed on the pattern after wiring the insulating coated wires. A method for manufacturing a multi-wire wiring board, comprising the step of applying an insulating ink that does not have catalytic properties to electroless plating over the entire area on an insulating resin layer.
JP13259582A 1982-07-29 1982-07-29 Method of producing multiwire circuit board Pending JPS5922396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13259582A JPS5922396A (en) 1982-07-29 1982-07-29 Method of producing multiwire circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13259582A JPS5922396A (en) 1982-07-29 1982-07-29 Method of producing multiwire circuit board

Publications (1)

Publication Number Publication Date
JPS5922396A true JPS5922396A (en) 1984-02-04

Family

ID=15085010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13259582A Pending JPS5922396A (en) 1982-07-29 1982-07-29 Method of producing multiwire circuit board

Country Status (1)

Country Link
JP (1) JPS5922396A (en)

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