JPS6221289A - Mounted substrate - Google Patents

Mounted substrate

Info

Publication number
JPS6221289A
JPS6221289A JP16025185A JP16025185A JPS6221289A JP S6221289 A JPS6221289 A JP S6221289A JP 16025185 A JP16025185 A JP 16025185A JP 16025185 A JP16025185 A JP 16025185A JP S6221289 A JPS6221289 A JP S6221289A
Authority
JP
Japan
Prior art keywords
shape memory
memory alloy
conductor
board
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16025185A
Other languages
Japanese (ja)
Inventor
古川 道明
隆幸 沖永
大津 守
寛治 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP16025185A priority Critical patent/JPS6221289A/en
Publication of JPS6221289A publication Critical patent/JPS6221289A/en
Pending legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は実装基板に関し、特に、実装基板における導体
配線において電気的導通をとることを必要とする各配線
間の導通を簡単にとることを可能とする技術に関する。
[Detailed Description of the Invention] [Technical Field] The present invention relates to a mounting board, and in particular, it is possible to easily establish electrical continuity between each wiring that requires electrical continuity in conductor wiring on a mounting board. Regarding technology.

〔背景技術〕[Background technology]

電子機器は各種の部品の集合体であり、各部品を所定の
位置に固定する必要がある。この役割に果たす基板(5
ubstrate)には部品相互の間を、決められた導
通路で結び、相互配線パターンで結線する必要がある。
Electronic equipment is an assembly of various parts, and each part needs to be fixed in a predetermined position. The substrate that plays this role (5
It is necessary to connect the components with each other through predetermined conductive paths and with mutual wiring patterns.

この相互配線パターンは上記の基板上に作られているこ
とが多い。
This mutual wiring pattern is often made on the above-mentioned substrate.

基板としては、一般に、樹脂基板とセラミック基板とが
主なるものである。樹脂基板は一般に印刷配線板、プリ
ント板などとよばれるもので、フェノール、エポキシ樹
脂などの樹脂の積層板の上に鋼箔を張り、エツチングで
パターンを作成する。
Generally, the main substrates are resin substrates and ceramic substrates. Resin substrates are generally referred to as printed wiring boards or printed circuit boards, and are made by applying steel foil onto a laminated board of resin such as phenol or epoxy resin, and creating a pattern by etching.

セラミック基板は、主としてアルミナ粉末を成形、焼成
したもので、その上に、印刷蒸着、エツチングでパター
ンを作成する。
Ceramic substrates are mainly formed by molding and firing alumina powder, and patterns are created thereon by printing vapor deposition and etching.

Ap−ンの高密度化に伴なう多層基板においては、一般
に、樹脂基板の場合、薄い樹脂板上にパターンを形成し
、それらを何枚か積み重ね、加圧し、熱を加えて樹脂を
硬化させ、その後、必要な個所にドリルで穴(スルーホ
ール)をあけ、穴の内部に導体をつけ、各層のパターン
間の導通をはかる。
In the case of resin substrates, in general, in the case of multilayer substrates accompanying the increase in density of AP-N, a pattern is formed on a thin resin plate, several of them are stacked, pressure is applied, and heat is applied to harden the resin. After that, holes (through-holes) are drilled in the necessary locations, and conductors are attached inside the holes to establish continuity between the patterns on each layer.

当該多層基板には多層セラミック基板もある。The multilayer substrate also includes a multilayer ceramic substrate.

かかる基板においては、その配線の切断はレザー等を用
いてトリミングする等容易であシ、各種の処決があるが
、配線の接続は容易でなく、その処決例は少ない。例え
ばワイヤー等を用い接続する方法もあるが、その作業が
煩雑である。
In such a board, the wiring can be easily cut by trimming using a laser or the like, and there are various treatments, but connecting the wiring is not easy and there are few examples of such treatments. For example, there is a method of connecting using wires, etc., but the work is complicated.

また、工業調査会発行「電子材料JI981年7月号P
26にはパターン修正全上記の如きディスクリートワイ
ヤを張ることより行わずに、スクリーン印刷で絶縁イン
クをスルーホールを避けて印刷し、その上にCuインク
を用いて配線し、スルーホール部にはハンダを印刷する
方法が記載されているが、同様に煩雑とならざるを得な
い。
In addition, “Electronic Materials JI July 981 issue P.
For 26, all pattern corrections were not done by stretching discrete wires as described above, but by screen printing insulating ink avoiding the through holes, wiring using Cu ink on top of that, and soldering in the through holes. Although a method for printing is described, it is similarly complicated.

〔発明の目的〕 本発明の目的は、電気的導通を簡単に任意の場所にとる
ことができる技術を提供することにある。
[Object of the Invention] An object of the present invention is to provide a technique that allows electrical continuity to be easily established at any location.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。
The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、本発明では、形状記憶合金を含有した絶縁層
全配線基板上に形成しておき、導通全必要とする場合に
は、該絶縁層をスポット的に加熱するもので、形状記憶
合金が元の大なる記憶形状によび戻され、これにより、
導通全必要とする場所相互間を結びつけ、導通をとるこ
とができる。
That is, in the present invention, an insulating layer containing a shape memory alloy is formed entirely on the wiring board, and when full conductivity is required, the insulating layer is heated in spots, so that the shape memory alloy is the original material. is returned to the great memory shape of
It is possible to connect and establish continuity between the required locations.

〔実施例〕〔Example〕

次に、本発明を、図面に示す実施例に基づいて説明する
Next, the present invention will be explained based on embodiments shown in the drawings.

1Ic1図〜第3図は本発明による導通処決を示すモデ
ル図で、これら図にて、1は配線基板、2は導体、3は
下部導体である。さらに、該配線基板1上には導体パタ
ーン4が形成されている。
1Ic1 to 3 are model diagrams showing the conduction process according to the present invention. In these figures, 1 is a wiring board, 2 is a conductor, and 3 is a lower conductor. Furthermore, a conductive pattern 4 is formed on the wiring board 1.

第1図に示すように、配線基板1上に、該導体パターン
部4を除いて、全面に、形状記憶合金5を含有する絶線
層6を適宜の厚味で塗布する。
As shown in FIG. 1, a disconnection layer 6 containing a shape memory alloy 5 is applied to the entire surface of the wiring board 1, except for the conductor pattern portion 4, to an appropriate thickness.

該絶縁層6上から、第2図に示すように、赤外線スポッ
ト加熱7を行う。
Infrared spot heating 7 is performed from above the insulating layer 6, as shown in FIG.

スポット加熱は、導通全必要としない部分をマスクして
おくことにより行うことができる。
Spot heating can be performed by masking portions that do not require full conduction.

これにょ9、絶縁/1i16内の形状記憶合金5が加熱
され、戻の形状をよびもどされ、導体パターン4.4と
形状記憶合金5とが接触し、これら導体パターン4,4
の間が電気的に導通する。
At this point, the shape memory alloy 5 in the insulation/1i16 is heated and restored to its original shape, and the conductor pattern 4.4 and the shape memory alloy 5 come into contact with each other, and these conductor patterns 4,4
There is electrical continuity between the two.

形状記憶合金5としては、ある形状を記憶させておくと
、これを変形しても、一定の温度以上に加熱すると、記
憶したものとの形に戻ってしまう現象金示す各種の合金
が使用でき、例えばNi −T1系合金やAu−Cd、
In−Tl、Cu−Zn。
Shape memory alloys 5 can be made of various alloys that exhibit the phenomenon that if a certain shape is memorized, even if it is deformed, it will return to the memorized shape when heated above a certain temperature. , for example, Ni-T1 alloy, Au-Cd,
In-Tl, Cu-Zn.

Cu−8n、Ni −Al系合金などが例示される。Examples include Cu-8n and Ni-Al alloys.

その形態の具体例としては、第4図に示すような、リン
グ状の形状記憶合金を、第5図に示すように、縮小した
、形の形状記憶合金となしておき、その加熱により、も
との大なるリング状の形状記憶合金となるものが挙げら
れる。
As a specific example of this form, a ring-shaped shape memory alloy as shown in FIG. 4 is made into a reduced shape shape memory alloy as shown in FIG. 5, and by heating it, Examples include large ring-shaped shape memory alloys.

絶縁層6を構成する絶縁材料としては各種のもの全使用
することができるが、例えばシリコーンゴムを使用する
ことが好ましい。
Although all kinds of insulating materials can be used as the insulating material constituting the insulating layer 6, it is preferable to use silicone rubber, for example.

この絶縁材料は、通常は、各導体パターン4゜4間を絶
縁し、導通を必要とする場合には当該形状記憶合金5の
広が1妨げような材料であることが好ましく、例えば、
液状(ペースト状)で、赤外線加熱により極端な加熱硬
化を起さないような、付加硬化型のシリコーンゴムが使
用される。
This insulating material is preferably a material that normally insulates each conductor pattern 4, 4, and prevents the spread of the shape memory alloy 5 when continuity is required. For example,
Addition-curing silicone rubber is used, which is liquid (paste-like) and does not undergo extreme thermal curing by infrared heating.

次に、第6図〜第9図により、本発明接続技術を詳述す
る。
Next, the connection technology of the present invention will be explained in detail with reference to FIGS. 6 to 9.

第6図に示すように、多層配線基板8上に導体部9を形
成し、第7図に示すように、核導体部9の頂面と同一平
面上に位置するように、形状記憶合金5を含有した絶縁
/16t−形成し、導通全必要とする導体部9,9間の
画線絶縁層6を赤外線スポット加熱すると、当該絶縁層
6内部で形状記憶合金5が拡大し導通がとられる(第8
図)。
As shown in FIG. 6, a conductor part 9 is formed on a multilayer wiring board 8, and as shown in FIG. When the insulation layer 6 between the conductor portions 9 and 9 that requires full conduction is heated with an infrared spot, the shape memory alloy 5 expands inside the insulation layer 6 and conduction is established. (8th
figure).

第9図は第8図A部の拡大説明図で、導通を必要とする
各導体部9,9が、形状記憶合金5を介して導通し、各
導体部9,9の下部に形成されたスルーホール中の導体
10.10間にも導通がはかられる。
FIG. 9 is an enlarged explanatory view of part A in FIG. 8, in which the conductor parts 9, 9 that require conduction are electrically connected through the shape memory alloy 5, and are formed at the bottom of each conductor part 9, 9. Continuity is also established between the conductors 10 and 10 in the through hole.

次に、第10図〜第11−に示す本発明の他の実施例全
説明する。
Next, other embodiments of the present invention shown in FIGS. 10 to 11 will be explained.

この実施例は、第10図に示すような、導体パターン1
1が形成された基板12上に、第11図に示すように形
状記憶合金5を含有した絶縁層6を塗布し、前記実施例
と同様にして赤外線スポット加熱全行なって成る例を示
す。第12図はこのようにして製せられた配線基板13
の一例を示す。
In this embodiment, a conductor pattern 1 as shown in FIG.
As shown in FIG. 11, an insulating layer 6 containing a shape memory alloy 5 is coated on a substrate 12 on which a shape memory alloy 5 is formed, and infrared spot heating is performed in the same manner as in the previous embodiment. FIG. 12 shows a wiring board 13 manufactured in this way.
An example is shown below.

本発明に使用される配線基板や多層基板については例え
ば樹脂封止基板やセラミック基板音用いることができる
As for the wiring board and multilayer board used in the present invention, for example, a resin-sealed board or a ceramic board can be used.

導体パターンやスルーホールにおける導体の形成方法に
ついては、周知のメタライゼーション(膜形成技術)や
メッキ膜形成技術などを用いることができる。
As for the method of forming the conductor in the conductor pattern and through-hole, well-known metallization (film formation technology), plating film formation technology, etc. can be used.

〔効 果〕〔effect〕

本発明によれば、形状記憶合金を利用することによυ、
電気的導通が簡単に任意な場所にとれその工業的意義は
大なるものがある。
According to the present invention, by using a shape memory alloy, υ,
Electrical continuity can be easily established at any location, and its industrial significance is great.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。
Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

〔利用分野〕[Application field]

本発明はプリント配線基板やハイブリッド基板など各棟
の実装基板に適用することができ、パッケージベースや
マザーボードなど配線間や端子間など電気的導通を必要
とする場合全般に適用することができる。
The present invention can be applied to mounting boards for each building, such as printed wiring boards and hybrid boards, and can be applied to all cases where electrical continuity is required, such as between wires or between terminals, such as package bases and motherboards.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第3図は本発明の詳細な説明するモデル図で、
第1図は形状記憶合金を含有する絶縁層塗布工程、第2
図は加熱工程、第3図は導通工程を示し、 第4図は形状記憶合金の加熱後の形態説明図、第5図は
同加熱前の形態説明図、 第6図〜第8図は本発明による実装基板の形成工程の説
明図、第6図は導体部形成工程、第7図は絶縁層形成工
程、第8図は導通工程、第9図は第8図A部拡大断面図
、 第10図〜第11図は本発明の他の実施例の説明図で、
第10図は基板説明図、第11図は当該基板上への絶縁
層形成工程説明図、 第12図は本発明による実装基板の一例平面図である。 1・・・配線基板、2・・・導体、3・・・下部導体、
4・・・導体パターン、5・・・形状記憶合金、6・・
・絶縁層、7・・・スポット加熱、8・・・多層配線基
板、9・・・導体部、10・・・スルホール導体、11
・・・導体パターン、第   1  図 第  3  図 第  4  図    第  5  間第   6  
図 グ 第  7  図 第  8  図 グ 第  9  図
Figures 1 to 3 are model diagrams explaining the present invention in detail.
Figure 1 shows the process of applying an insulating layer containing a shape memory alloy;
The figure shows the heating process, Figure 3 shows the conduction process, Figure 4 is an explanatory diagram of the shape of the shape memory alloy after heating, Figure 5 is an explanatory diagram of the shape before heating, and Figures 6 to 8 are the main figures. An explanatory diagram of the forming process of the mounting board according to the invention, FIG. 6 is a conductor part forming process, FIG. 7 is an insulating layer forming process, FIG. 8 is a conduction process, FIG. 9 is an enlarged sectional view of part A in FIG. 8, 10 to 11 are explanatory diagrams of other embodiments of the present invention,
FIG. 10 is an explanatory diagram of a substrate, FIG. 11 is an explanatory diagram of a step of forming an insulating layer on the substrate, and FIG. 12 is a plan view of an example of a mounting substrate according to the present invention. 1... Wiring board, 2... Conductor, 3... Lower conductor,
4... Conductor pattern, 5... Shape memory alloy, 6...
- Insulating layer, 7... Spot heating, 8... Multilayer wiring board, 9... Conductor portion, 10... Through-hole conductor, 11
...Conductor pattern, Figure 1 Figure 3 Figure 4 Figure 5 Interval 6
Figure 7 Figure 8 Figure 9

Claims (1)

【特許請求の範囲】 1、実装基板における所定の配線間又は端子間等その電
気的導通をとることを必要とする相互間の当該導通を形
状記憶合金によりとって成ることを特徴とする実装基板
。 2、実装基板がプリント配線基板で当該配線基板上に導
体配線層を突設し、当該配線層を除く部分に形状記憶合
金を含有した絶縁層を形成後、導通をとることを必要と
する前記導体配線間を加熱し、形状記憶合金により導通
をとって成る、特許請求の範囲第1項記載の実装基板。
[Claims] 1. A mounting board characterized in that electrical continuity between predetermined wirings or terminals on the mounting board that requires electrical continuity is provided by a shape memory alloy. . 2. The mounting board is a printed wiring board, and a conductive wiring layer is provided protrudingly on the wiring board, and an insulating layer containing a shape memory alloy is formed on the part excluding the wiring layer, and then conduction is established. 2. The mounting board according to claim 1, wherein the conductor wirings are heated and electrically connected by a shape memory alloy.
JP16025185A 1985-07-22 1985-07-22 Mounted substrate Pending JPS6221289A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16025185A JPS6221289A (en) 1985-07-22 1985-07-22 Mounted substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16025185A JPS6221289A (en) 1985-07-22 1985-07-22 Mounted substrate

Publications (1)

Publication Number Publication Date
JPS6221289A true JPS6221289A (en) 1987-01-29

Family

ID=15710961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16025185A Pending JPS6221289A (en) 1985-07-22 1985-07-22 Mounted substrate

Country Status (1)

Country Link
JP (1) JPS6221289A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104412112A (en) * 2012-06-18 2015-03-11 株式会社Isc Test socket including conductive particles in which through-holes are formed and method for manufacturing same
US10369498B2 (en) 2012-05-07 2019-08-06 Toyota Boshoku Kabushiki Kaisha Oil deterioration suppressing apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10369498B2 (en) 2012-05-07 2019-08-06 Toyota Boshoku Kabushiki Kaisha Oil deterioration suppressing apparatus
CN104412112A (en) * 2012-06-18 2015-03-11 株式会社Isc Test socket including conductive particles in which through-holes are formed and method for manufacturing same
JP2015524145A (en) * 2012-06-18 2015-08-20 株式会社アイエスシーIsc Co., Ltd. Inspection socket having conductive particles with through holes formed therein and method for manufacturing the same
US9759742B2 (en) 2012-06-18 2017-09-12 Isc Co., Ltd. Test socket including conductive particles in which through-holes are formed and method for manufacturing same

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