JPS58115885A - Method of producing circuit board - Google Patents

Method of producing circuit board

Info

Publication number
JPS58115885A
JPS58115885A JP21463181A JP21463181A JPS58115885A JP S58115885 A JPS58115885 A JP S58115885A JP 21463181 A JP21463181 A JP 21463181A JP 21463181 A JP21463181 A JP 21463181A JP S58115885 A JPS58115885 A JP S58115885A
Authority
JP
Japan
Prior art keywords
conductive
circuit pattern
circuit board
board
producing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21463181A
Other languages
Japanese (ja)
Other versions
JPS6031118B2 (en
Inventor
幸弘 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP21463181A priority Critical patent/JPS6031118B2/en
Publication of JPS58115885A publication Critical patent/JPS58115885A/en
Publication of JPS6031118B2 publication Critical patent/JPS6031118B2/en
Expired legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は配線基板に係り、特に卓上計算機等に採用して
好適な配線基板の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring board, and more particularly to a method of manufacturing a wiring board suitable for use in desktop computers and the like.

従来、印刷回路に於ては、銅張積層板等をホトエツチン
グして所望の回路パターンを形成し、導電箔の腐食を防
止するために、導電箔上を全て金メッキする方法が行な
われている。しかしながら、この方法では金等の高価な
材料を使用せねばならず、コスト高となる欠点があった
。これを改善するために、第1図のように絶縁基板1上
にスクリーン印刷により銀と合成樹脂より成る導電ペー
スト2によって回路パターンを形成し、しかる後該回路
パターンの導電系並びに絶縁基板の全面にエポキシ樹脂
等の樹脂系被膜3をオーバーコートし銀皮膜の腐食を防
止し、かつ銀ペースト中の銀粒子のマイグレーションの
発生を防止する方法が行なわれていた。
Conventionally, in printed circuits, a method has been used in which a copper-clad laminate or the like is photoetched to form a desired circuit pattern, and the entire surface of the conductive foil is plated with gold to prevent corrosion of the conductive foil. However, this method requires the use of expensive materials such as gold, resulting in high costs. In order to improve this, as shown in Figure 1, a circuit pattern is formed on an insulating substrate 1 by screen printing using a conductive paste 2 made of silver and synthetic resin, and then the conductive system of the circuit pattern and the entire surface of the insulating substrate are A method has been used in which a resin film 3 such as epoxy resin is overcoated to prevent corrosion of the silver film and to prevent migration of silver particles in the silver paste.

しかし、この方法は銀ペーストの重大な欠点である半田
性の悪い点から回路パターンを外部に接続する際に、半
田付接続もしくは接点のコンタクトとしては使用できず
、とくに卓上計算機等のキーボードに於ける回路接点と
して使用することができないという欠点があった。
However, this method cannot be used as a solder connection or as a contact when connecting a circuit pattern to the outside because of its poor solderability, which is a major drawback of silver paste. The disadvantage was that it could not be used as a circuit contact.

それゆえ、このような欠点を改善するために1、第2図
のように銀ペーストの導電系回路パターンにカーボン系
導電塗料4による保護皮膜が行なわれた。しかしこの方
法は銀ペーストによる回路パターンの印刷と保護皮膜と
の間に多少のずれが避けられないので、回路パターンを
形成する導電箔相互の間隔を十分に狭くすることが困難
で、特に小型の回路基板上に多くの導電条を形成するこ
とが困難となるなどの欠点があった。
Therefore, in order to improve such drawbacks, a protective film of a carbon-based conductive paint 4 was applied to the silver paste conductive circuit pattern as shown in FIGS. 1 and 2. However, this method inevitably causes some misalignment between the printed circuit pattern using silver paste and the protective film, making it difficult to sufficiently reduce the distance between the conductive foils that form the circuit pattern. There were drawbacks such as difficulty in forming many conductive strips on the circuit board.

本発明は上記従来の諸欠点を除去する為になされたもの
で、とくに導電パターンを形成する銀ペースト並びに絶
縁基板の全面に、基板と垂直方向にのみ導通する金属粉
末を配合した合成樹脂より成る被膜を形成することによ
り、オーバーコート処理が簡単で導電箔相互の間隔を十
分に狭くすることができ、半田性の悪い銀ペーストの欠
点を除去し、マイグレーションのない特に小型の回路基
板に適した配線基板の製造方法を提供したものである。
The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and is made of a synthetic resin mixed with a silver paste forming a conductive pattern and a metal powder that is conductive only in the direction perpendicular to the substrate on the entire surface of the insulating substrate. By forming a film, the overcoat process is easy and the distance between the conductive foils can be sufficiently narrowed, eliminating the disadvantages of silver paste with poor solderability, making it especially suitable for small circuit boards without migration. The present invention provides a method for manufacturing a wiring board.

以下本発明の一実施例を図面に従って説明すると、第3
図に示すように絶縁基板1上にスクリーン印刷等により
銀と合成樹脂より成る導電ペースト2によって回路パタ
ーンを形成し、しかる後、フェノール樹脂、エポキシ樹
脂等の適宜な合成樹脂内に針状の金属粉末、たとえば鉄
(Fe)粉を配合 画した被膜5を回路パターン並びに絶縁基板の全面に印
刷形成して完成する。この場合、基板と垂直(たて)方
向のみに導通性をもたせ、基板と水平(よこ)方向に導
通性をもたせなし鷺即ち各回路パターン或いは導電条の
各接続を許さないようにするために、鉄(Fe)粉であ
れば磁界を加えて基板と垂直方向にのみ導通性をもたせ
、一方水平(よこ)方向の導通がないようにFe粉の密
度を下げ、針状鉄粉の側面を樹脂で絶縁被覆するもので
ある。このようにすれば、回路パターンを含む基板全面
をオーバーコートしても、銀ペーストより形成される配
線パターンはオーバーコート樹脂より直接電極として自
由に取り出すことが出来るから、小型卓上計算機等の回
路接点としての使用が可能である。
One embodiment of the present invention will be described below with reference to the drawings.
As shown in the figure, a circuit pattern is formed on an insulating substrate 1 using a conductive paste 2 made of silver and synthetic resin by screen printing or the like, and then a needle-shaped metal is placed in a suitable synthetic resin such as phenol resin or epoxy resin. A coating 5 containing powder, for example iron (Fe) powder, is printed and formed on the circuit pattern and the entire surface of the insulating substrate. In this case, in order to provide conductivity only in the vertical (vertical) direction to the board, and not to provide conductivity in the horizontal (horizontal) direction to the board, that is, to prevent connections between circuit patterns or conductive strips. In the case of iron (Fe) powder, a magnetic field is applied to provide conductivity only in the vertical direction to the substrate, while the density of the Fe powder is lowered so that there is no conduction in the horizontal direction, and the sides of the needle-shaped iron powder are It is insulated and coated with resin. In this way, even if the entire surface of the board including the circuit pattern is overcoated, the wiring pattern formed from the silver paste can be freely taken out directly from the overcoat resin as an electrode, making it suitable for circuit contacts such as small desk calculators. It can be used as

以上説明したように本発明によれば、基板と垂。As explained above, according to the present invention, the substrate and the vertical plate are connected to each other.

な 直方向にのみ導通性を有する金属粉末を配向した合成樹
脂より成る被膜を接点部などの回路パターンならびに絶
縁基板・に施せばよく、オーバーコート処理工程が簡単
で多数の導電条が接近して形成されても基板と水平方向
への導通がないので導電条の相互間隔を十分に狭く形成
することができ、導電条間にマイグレーシランが発生す
ることもなく、回路パターンを外部に接続することも可
能で、特に卓上計算機等の回路基板に好適な廉価な配線
基板を提供しうるという効果がある。
All that is required is to apply a coating made of synthetic resin containing oriented metal powder that has conductivity only in the perpendicular direction to circuit patterns such as contacts and insulating substrates. Even if the conductive strips are formed, there is no horizontal conduction with the substrate, so the mutual spacing between the conductive strips can be formed sufficiently narrow, and the circuit pattern can be connected to the outside without generating migration silane between the conductive strips. This is particularly effective in providing an inexpensive wiring board suitable for circuit boards of desktop computers and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は従来の配線基板の製造方法を示す断
面図、第3図は本発明による配線基板の製造方法の一例
を示す断面図である。 図中、  l:絶縁基板  2:導電ペースト5:金属
粉末を配向した合成樹脂よりなる被膜代理人 弁理士 
福 士 愛 彦 第1図 第2図 第3図
1 and 2 are cross-sectional views showing a conventional method for manufacturing a wiring board, and FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to the present invention. In the figure, l: insulating substrate 2: conductive paste 5: coating made of synthetic resin with oriented metal powder Patent attorney
Aihiko Fukushi Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1、 導電パターンを形成する導電ペースト並びに所定
の絶縁基板の全面に、基板と垂直方向にのみ導通する金
属粉末を配合した合成樹脂より成る被膜を形成したこと
を特徴とする配線基板の製造方法。
1. A method for manufacturing a wiring board, characterized in that a conductive paste forming a conductive pattern and a coating made of a synthetic resin mixed with metal powder that is conductive only in a direction perpendicular to the board are formed on the entire surface of a predetermined insulating board.
JP21463181A 1981-12-28 1981-12-28 Manufacturing method of wiring board Expired JPS6031118B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21463181A JPS6031118B2 (en) 1981-12-28 1981-12-28 Manufacturing method of wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21463181A JPS6031118B2 (en) 1981-12-28 1981-12-28 Manufacturing method of wiring board

Publications (2)

Publication Number Publication Date
JPS58115885A true JPS58115885A (en) 1983-07-09
JPS6031118B2 JPS6031118B2 (en) 1985-07-20

Family

ID=16658932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21463181A Expired JPS6031118B2 (en) 1981-12-28 1981-12-28 Manufacturing method of wiring board

Country Status (1)

Country Link
JP (1) JPS6031118B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59141286A (en) * 1983-02-01 1984-08-13 株式会社精工舎 Circuit board
JPS60101992A (en) * 1983-11-08 1985-06-06 株式会社精工舎 Circuit board and method of producing same
JPS60133789A (en) * 1983-12-21 1985-07-16 株式会社精工舎 Circuit board and method of producing same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59141286A (en) * 1983-02-01 1984-08-13 株式会社精工舎 Circuit board
JPS60101992A (en) * 1983-11-08 1985-06-06 株式会社精工舎 Circuit board and method of producing same
JPH0336318B2 (en) * 1983-11-08 1991-05-31 Seikosha Kk
JPS60133789A (en) * 1983-12-21 1985-07-16 株式会社精工舎 Circuit board and method of producing same

Also Published As

Publication number Publication date
JPS6031118B2 (en) 1985-07-20

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