JPS5922397A - Method of producing multiwire circuit board - Google Patents

Method of producing multiwire circuit board

Info

Publication number
JPS5922397A
JPS5922397A JP13259682A JP13259682A JPS5922397A JP S5922397 A JPS5922397 A JP S5922397A JP 13259682 A JP13259682 A JP 13259682A JP 13259682 A JP13259682 A JP 13259682A JP S5922397 A JPS5922397 A JP S5922397A
Authority
JP
Japan
Prior art keywords
layer
insulating
wire
wiring board
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13259682A
Other languages
Japanese (ja)
Inventor
山崎 正踐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP13259682A priority Critical patent/JPS5922397A/en
Publication of JPS5922397A publication Critical patent/JPS5922397A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明はマルチワイヤ配線板の製造方法に関し、特にス
ルホールめっき工程中に使用するめつきレジスト層の形
成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multi-wire wiring board, and particularly to a method for forming a plating resist layer used during a through-hole plating process.

近年、ICをはじめとする実装部品の小型化、高集積化
の発展に伴ない、印刷配線板に対しても配線パターンの
高精度化、高密度化などの要求が強くなっている。さら
にニーズの多様化につれて、生産の多品種、少量化傾向
も顕著になってきている。
In recent years, as mounting components such as ICs have become smaller and more highly integrated, there has been a growing demand for higher precision and higher density wiring patterns for printed wiring boards. Furthermore, as needs become more diversified, there is a growing tendency to produce a greater variety of products in smaller quantities.

マルチワイヤ配線板は絶縁被覆を、配線基板上の絶縁性
接着剤層上に交差配線することにより信号回路を形成し
ている。
A multi-wire wiring board forms a signal circuit by cross-wiring an insulating coating on an insulating adhesive layer on a wiring board.

従って印刷配線板の製作上必要であった原画、写真など
のアートワークを必要としないばかりか実装の高密度化
を容易にし、多品種少数生産におけるコストバーフォマ
ンスの改善に寄与している。
Therefore, not only does artwork such as original drawings and photographs that are necessary in the production of printed wiring boards become unnecessary, but it also facilitates high-density mounting, contributing to improved cost efficiency in high-mix, low-volume production.

この種の従来マルチワイヤ配線板の代表的な一例を第1
図および第2図を参照して説明する。第1図(a)の如
く無゛亀解めっき用触媒を含む絶縁基板■の上に必要に
応じて例えば電源)−1接地層として1史用することが
できるようにバタン化した銅箔層2を片面又は両面に形
成し、次に第1図(1〕)の如く、絶轍基板1および銅
箔層2に接して無lイ解めっき用触媒を含む接着層3を
形成した後、81N1図(C)の如く1ぎ号回路として
の絶縁被覆ワイヤ4の所望回路パターンを、例えば数値
制御式自動布線装置により、接着層3に布線固着させ、
さらに第1図(d)の如く布線固着した絶縁被覆ワイヤ
4による回路パターンを保護し、かつ固着を確実にする
ために無電解めっき#J触媒を含むプリプレグをイ責層
接着′することにより無電解めっきに対して触媒性を有
する絶縁層(以下触媒性絶縁層と称す)5を形成する。
A typical example of this type of conventional multi-wire wiring board is shown in the first example.
This will be explained with reference to the figures and FIG. As shown in Fig. 1(a), a copper foil layer is formed on an insulating substrate (2) containing a catalyst for non-glare plating, if necessary, so that it can be used as a power supply (1) -1 (ground) layer. 2 is formed on one or both sides, and then, as shown in FIG. 1 (1), after forming an adhesive layer 3 containing a catalyst for no-liquid plating in contact with the rutted substrate 1 and the copper foil layer 2, 81N1 A desired circuit pattern of the insulated wire 4 as the No. 1 circuit is fixed to the adhesive layer 3 using, for example, a numerically controlled automatic wiring device, as shown in FIG.
Furthermore, as shown in FIG. 1(d), in order to protect the circuit pattern formed by the insulated wire 4 fixed to the wiring and to ensure the fixation, a prepreg containing electroless plating #J catalyst is bonded with an irradiation layer. An insulating layer 5 having catalytic properties for electroless plating (hereinafter referred to as catalytic insulating layer) is formed.

さらに外表面に無電解めっきに対して触媒性を有しない
非整合マスク層(以下マスク層と称す)6を形成した後
、第1図(e)の如く所望の位置に絶縁被障ワイヤおよ
び銅箔層2を横切るように貫通孔7を穿設し、絶縁被覆
ワイヤ4および銅箔層2の少なくとも一部を貫通孔7の
内面に露出させた後、無電解めっき液に浸漬することに
より貫通孔7の壁面に金属導体層8を形成してスルポー
ルとし、第1図(f)の如くマスク層6を除去して第2
図に示すようなマルチワイヤ配線板を形成するものであ
った。このようなマルチワイヤ配線板の従来の製造工程
に於けるめっきレジスト層としてのマスク層6は、めっ
き終了後に剥離する事を前提として加工を施していた。
Furthermore, after forming a non-conforming mask layer (hereinafter referred to as mask layer) 6 that does not have catalytic properties against electroless plating on the outer surface, insulated wires and copper are placed at desired positions as shown in FIG. 1(e). A through hole 7 is formed across the foil layer 2, and at least a portion of the insulated wire 4 and the copper foil layer 2 are exposed on the inner surface of the through hole 7, and then penetrated by dipping in an electroless plating solution. A metal conductor layer 8 is formed on the wall surface of the hole 7 to form a through pole, and the mask layer 6 is removed as shown in FIG. 1(f).
A multi-wire wiring board as shown in the figure was formed. In the conventional manufacturing process of such a multi-wire wiring board, the mask layer 6 as a plating resist layer was processed on the premise that it would be peeled off after plating was completed.

マスク層6はポリエチレンシートの片面に粘着性の樹脂
層を塗布したもので、基板への貼り合わせは熱圧着と言
う手段によっていたが、温度55〜70°0と言う高温
の無電解めっき浴に長時間曝されたり、孔明は時の機械
的なストレス等に依り、時として安定なめっきレジスト
層としての働きが維持出来ず、部分的なマスクのハガレ
や破損の為に、めっき不可部分への、めっき析出が生じ
る事が有った。
The mask layer 6 is a polyethylene sheet coated with an adhesive resin layer on one side, and was bonded to the substrate by a method called thermocompression bonding, but it was applied to a high-temperature electroless plating bath at a temperature of 55 to 70 degrees. Due to long-term exposure or mechanical stress, the plating resist layer is sometimes unable to maintain its function as a stable plating resist layer, resulting in partial peeling or damage of the mask, resulting in unplated areas being damaged. , plating precipitation may occur.

本発明はこの様な従来の欠点を改良したマルチワイヤ配
線板の製造方法を提供することにある。
The object of the present invention is to provide a method for manufacturing a multi-wire wiring board that overcomes these conventional drawbacks.

本発明によれば絶縁基板上に絶縁被覆ワイヤを布線固着
して回路パタンを形成すると共にワイヤの終端部を基板
上に穿設された貫通孔の孔壁上に無電解めっきのスルホ
ール導電層を形成して接続されてなるマルチワイヤ配線
板の製造方法において、絶縁被覆ワイヤを布線した後の
パターン上に無電解めっきに対して触媒性を有する絶縁
性樹脂層の積層形成が終了した基板に対して、絶縁性樹
脂層上のスルホールランドに対応する部分以外を無電解
めっきに対して触媒性を有しない絶縁性インクを塗糊す
る工程を含むことを特徴とするマルチワイヤ配線板の製
造方法が得られる。
According to the present invention, a circuit pattern is formed by wiring and fixing an insulating coated wire on an insulating substrate, and the terminal end of the wire is coated with an electroless-plated through-hole conductive layer on the wall of a through-hole drilled on the substrate. In the manufacturing method of a multi-wire wiring board formed by forming and connecting insulating coated wires, a substrate on which an insulating resin layer having catalytic properties for electroless plating has been laminated on a pattern after wiring insulation coated wires. The production of a multi-wire wiring board is characterized in that it includes a step of applying an insulating ink that does not have catalytic properties to electroless plating to areas other than the portions corresponding to the through-hole lands on the insulating resin layer. method is obtained.

以下、本発明を第3図を参照して説明する。The present invention will be explained below with reference to FIG.

第3図は本発明の一実施例を示す断面図である。FIG. 3 is a sectional view showing an embodiment of the present invention.

第3図(a)は前述した従来例の第1図(a)ないし第
1図(C)と同様にして製造した中間工程の配線板の状
帽を示すものである。この配線板の表裏両面に無′屯解
めっきに対して触媒性を有するプリプレグの所望枚数を
重ねた構成体の上下両面を十分な剛性を有する例えばス
テンレス鋼で作った平面板(図示省略)にて挾持し、こ
の平面板構成体を加熱、加圧して触媒性絶縁層5を形成
する。この触媒性絶縁層5の形成の後に触媒性絶縁層5
の外側に無電解めっきに対して触媒性を有しない熱硬化
性のインクを防用して、触媒性絶縁層5上で、後述すル
スルホール孔明は以降の工程でスルホールのランドが形
成される部分に対しては逃げ部分を有する印、刷パター
ンによりスクリーン印刷を実施する。
FIG. 3(a) shows a wiring board in an intermediate step manufactured in the same manner as in FIGS. 1(a) to 1(C) of the conventional example described above. A desired number of sheets of prepreg having catalytic properties for non-removal plating are stacked on both sides of the wiring board, and the upper and lower surfaces of the structure are covered with flat plates (not shown) having sufficient rigidity and made of stainless steel, for example. The catalytic insulating layer 5 is formed by heating and pressurizing the flat plate structure. After the formation of this catalytic insulating layer 5, the catalytic insulating layer 5
A thermosetting ink that does not have catalytic properties is applied to the outside of the electroless plating layer, and on the catalytic insulating layer 5, through-hole lands are formed in subsequent steps. For the part, screen printing is performed using printing and printing patterns that have relief parts.

このスクリーン印刷によるインクの塗糊の後、これを加
熱等の手段により硬化させる。
After applying the ink by screen printing, it is cured by means such as heating.

以上の方法により第3図(b)のごとく無電解めっきに
対して触媒性を有しない絶縁層(以下非触媒性絶縁j−
と称す)9を形成する。
By the above method, as shown in Fig. 3(b), an insulating layer (hereinafter non-catalytic insulating
9).

次に第3図(C)のごとく、所望の位置に絶縁被覆ワイ
ヤ4および銅箔層2を横切るように貫通孔7を穿設し、
絶縁被覆ワイヤ4および銅箔層2の少なくとも一部を貫
通孔7の内壁面に露出させた後無電解めっき液に浸漬す
ることによp貫通孔7の内壁面に1第3図(d)のごと
く金属導体層8を形成した。
Next, as shown in FIG. 3(C), a through hole 7 is bored at a desired position so as to cross the insulated wire 4 and the copper foil layer 2,
At least a part of the insulated wire 4 and the copper foil layer 2 are exposed on the inner wall surface of the through hole 7, and then immersed in an electroless plating solution to coat the inner wall surface of the through hole 7. A metal conductor layer 8 was formed as follows.

非触媒性絶縁層9は基板内外層と同様に安定、且つ、強
固に形成されているため、従来のマスク層6の使用時に
見られた破損等によるめっき不可部分へのめっき析出が
ないので、めっきレジスト層としての出所み後において
も基材の保護用として製品の一部を構成させても何ら支
障がないばかりか、残留による基板に対する保護体とし
ての効果は大なるものがらる。
Since the non-catalytic insulating layer 9 is formed to be stable and strong like the inner and outer layers of the substrate, there is no plating precipitation on areas that cannot be plated due to damage etc. that was observed when using the conventional mask layer 6. Even after being used as a plating resist layer, there is no problem in forming a part of the product to protect the base material, and the residual material is highly effective as a protector for the base material.

以上、本発明により、次の効果が143られた。As described above, the following effects have been achieved by the present invention.

(1)  めっき時に従来のめっきレジス) 11&以
−にの密着性を維持することが出来るため、めっき導体
によるブリッジの発生や、絶縁不甑等の発生が低減出来
た。
(1) Since it is possible to maintain the adhesion of the conventional plating resist (11&) during plating, the occurrence of bridging due to the plating conductor and the occurrence of insulation debris etc. can be reduced.

(11)従来のようなめっきレジスト層の除去が不要な
ため工数低減及びリードタイム短縮のメリットは言うに
及ばず、除去時に多発していたに板表面の破損を皆無に
出来た。
(11) Since there is no need to remove the plating resist layer as in the conventional method, there are not only advantages of reduced man-hours and lead time, but also no damage to the plate surface, which often occurs during removal.

(iii)  部品実装時以降の基板の機械的及び耐環
境的安定性が向上する。
(iii) The mechanical and environmental stability of the board after component mounting is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f)は従来のマルチワイヤ配線板の製
造工程の断面図、第2図は第1図の斜視図。第3図(a
)〜(d)は本発明のマルチワイヤ配線板の製造工程の
断面図。 ■・・・・・・絶縁基板、2・・・・・・内層鋼箔層、
3・・・・・・接着層、4・・・・・・絶縁被覆ワイヤ
、5・・・・・・触媒性絶縁層、6・・・・・・マスク
層、7・・・・・・貫通孔、8・・・・・・金属導体層
、9・・・・・・非触媒性絶縁層。 猶1図 ゛” / #2図
1(a) to 1(f) are cross-sectional views of the manufacturing process of a conventional multi-wire wiring board, and FIG. 2 is a perspective view of FIG. 1. Figure 3 (a
) to (d) are cross-sectional views of the manufacturing process of the multi-wire wiring board of the present invention. ■...Insulating substrate, 2...Inner steel foil layer,
3... Adhesive layer, 4... Insulating coated wire, 5... Catalytic insulating layer, 6... Mask layer, 7... Through hole, 8... Metal conductor layer, 9... Non-catalytic insulating layer. Figure 1 ゛” / Figure #2

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板上に絶縁被覆ワイヤを布線して回路パタンを形
成すると共に前記ワイヤの終端部を基板上に設けられた
貫通孔の孔壁上に無電解めっきのスルホール導電層を形
成して接続されてなるヤルチワイヤ配線板の製造方法に
おいて、前記絶縁被覆ワイヤを布線した後のパターン上
に無電解めっきに対して触媒性を有する絶縁性樹脂層の
積層形成が終了した基板に対して、前記絶縁性樹脂層上
のスルホールランドに対応する部分以外を無電解めっき
に対して触媒性を有しない絶縁性インクを塗糊する工程
を含むことを特徴とするマルチワイヤ配線板の製造方法
A circuit pattern is formed by wiring an insulated wire on an insulating substrate, and the terminal end of the wire is connected by forming an electroless-plated through-hole conductive layer on the wall of a through-hole provided on the substrate. In the method for manufacturing a Yaruchi wire wiring board, the insulating layer is applied to a substrate on which an insulating resin layer having catalytic properties for electroless plating has been laminated on the pattern after wiring the insulating coated wire. 1. A method for manufacturing a multi-wire wiring board, comprising the step of applying an insulating ink that does not have catalytic properties to electroless plating to areas other than those corresponding to through-hole lands on a polyurethane resin layer.
JP13259682A 1982-07-29 1982-07-29 Method of producing multiwire circuit board Pending JPS5922397A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13259682A JPS5922397A (en) 1982-07-29 1982-07-29 Method of producing multiwire circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13259682A JPS5922397A (en) 1982-07-29 1982-07-29 Method of producing multiwire circuit board

Publications (1)

Publication Number Publication Date
JPS5922397A true JPS5922397A (en) 1984-02-04

Family

ID=15085035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13259682A Pending JPS5922397A (en) 1982-07-29 1982-07-29 Method of producing multiwire circuit board

Country Status (1)

Country Link
JP (1) JPS5922397A (en)

Similar Documents

Publication Publication Date Title
US3742597A (en) Method for making a coated printed circuit board
JPH0240230B2 (en)
JPH05183259A (en) Manufacture of high density printed wiring board
US3850711A (en) Method of forming printed circuit
JPS5922397A (en) Method of producing multiwire circuit board
JPS63137498A (en) Manufacture of through-hole printed board
JPS5922396A (en) Method of producing multiwire circuit board
JPS6336598A (en) Manufacture of wiring board
JPS5922395A (en) Method of producing multiwire circuit board
JPS6355236B2 (en)
JPS648478B2 (en)
JPH05259614A (en) Resin filling method for printed wiring board
JPS6236900A (en) Manufacture of compound printed wiring board
JPS584999A (en) Method of producing printed circuit board
JPS6235692A (en) Printed wiring board
JPH0353796B2 (en)
JPS60124992A (en) Printed circuit board and method of producing same
JPS5877287A (en) Method of producing printed circuit board
JPS59232491A (en) Method of producing multilayer printed circuit board
JPS6221289A (en) Mounted substrate
JPS61226992A (en) Flexible circuit board with oxide insulated layer
JPS5961992A (en) Method of producing through hole printed circuit board
JPS6236896A (en) Manufacture of one-side through hole wiring board
JPH0851262A (en) Printed wiring board and its manufacturing method
JPS58121698A (en) Multilayer printed board