JPS59223040A - ル−プ伝送システムにおけるインテリジエント端末の二重系制御方式 - Google Patents

ル−プ伝送システムにおけるインテリジエント端末の二重系制御方式

Info

Publication number
JPS59223040A
JPS59223040A JP58095824A JP9582483A JPS59223040A JP S59223040 A JPS59223040 A JP S59223040A JP 58095824 A JP58095824 A JP 58095824A JP 9582483 A JP9582483 A JP 9582483A JP S59223040 A JPS59223040 A JP S59223040A
Authority
JP
Japan
Prior art keywords
loop transmission
data
dual
control method
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58095824A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0220189B2 (enrdf_load_html_response
Inventor
Hiroshi Matsumaru
松丸　宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58095824A priority Critical patent/JPS59223040A/ja
Publication of JPS59223040A publication Critical patent/JPS59223040A/ja
Publication of JPH0220189B2 publication Critical patent/JPH0220189B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/437—Ring fault isolation or reconfiguration

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
JP58095824A 1983-06-01 1983-06-01 ル−プ伝送システムにおけるインテリジエント端末の二重系制御方式 Granted JPS59223040A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58095824A JPS59223040A (ja) 1983-06-01 1983-06-01 ル−プ伝送システムにおけるインテリジエント端末の二重系制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58095824A JPS59223040A (ja) 1983-06-01 1983-06-01 ル−プ伝送システムにおけるインテリジエント端末の二重系制御方式

Publications (2)

Publication Number Publication Date
JPS59223040A true JPS59223040A (ja) 1984-12-14
JPH0220189B2 JPH0220189B2 (enrdf_load_html_response) 1990-05-08

Family

ID=14148152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58095824A Granted JPS59223040A (ja) 1983-06-01 1983-06-01 ル−プ伝送システムにおけるインテリジエント端末の二重系制御方式

Country Status (1)

Country Link
JP (1) JPS59223040A (enrdf_load_html_response)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5257744A (en) * 1975-11-07 1977-05-12 Hitachi Ltd Station control unit of data freeway
JPS54133859A (en) * 1978-04-08 1979-10-17 Toshiba Corp Backing-up method of electronic computer system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5257744A (en) * 1975-11-07 1977-05-12 Hitachi Ltd Station control unit of data freeway
JPS54133859A (en) * 1978-04-08 1979-10-17 Toshiba Corp Backing-up method of electronic computer system

Also Published As

Publication number Publication date
JPH0220189B2 (enrdf_load_html_response) 1990-05-08

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