JPS59222883A - Crt display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a CRT display control device, and particularly to a CRT display control device.
The present invention relates to a CRT display control device that can perform high-speed and detailed screen control using hardware without depending on a PU program.

In conventional CRT display control devices, video data (dot pattern,
data) is temporarily stored in a video memory, and is read out from the video memory in synchronization with the timing of rask scanning of the CRT and output to the CRT. Conventionally, when performing complete display control on a CRT, (1) changing the video data on the video memory in the same area as the display area;
How to display this on a CRT and change the display screen, and (1)
There is a method of preparing a video memory larger than the display area, specifying only the start address of the display area, and changing the display screen by changing the start address.

However, in method (1) above, the memory contents are written under program control of the CPU, so the larger the amount of change, the slower the speed of change becomes.

Furthermore, in method (11) above, since a video memory larger than the display area is required, the memory capacity increases, and screen control within the display area, such as split scrolling, is difficult. In other words, when using a scroll function that sequentially moves all character strings or all character lines on the screen upward or downward, the characters displayed at the top (bottom line) disappear from the screen across all columns. Additionally, newly displayed characters are always on the bottom line (topmost). For example, even if there is a request to simultaneously display data and guidance display, or certain data and comparison data, and scroll only one of them, it is difficult to do so using conventional methods.

Purpose The purpose of the present invention is to improve the drawbacks of the conventional technology and to provide a CPU that can perform high-speed and fine-grained screen control, eliminates the intervention of the CPU, and improves the efficiency of the CPU.
An object of the present invention is to provide an RT display control device.

ffi? Growth Hereinafter, the configuration of the present invention will be explained using examples.

FIG. 1 is a block diagram of a CRT display control device showing an embodiment of the present invention.

In FIG. 1, 1 is the CPo that controls read/write of information in the RAM, 2 is the RAM that includes the main memory, video memory, and management table, and 3 is the CPU.
5 is a timing generator that controls the timing of each block; 6 is a counter (ADC) that passes the address in the management table to the main bus; 7 is a gate that connects the RAM and bus; is a counter (
VAC), 8 is a converter that converts the data from RAM 2 into parallel/serial data to make a video signal and passes it to the CRT.

The control device of the present invention transmits information specified by the CPU to the CRT.
In a control device equipped with a video ij' control section for displaying a video on the screen, a timing control section 5 for controlling timing, and a memory 2, a table storing display memory start addresses for each raster of a CRT for n rasters is stored in the memory 2. By incrementing and specifying the address of the table using the counter (ADC) 6, the video memory is accessed using that address and the video data for each raster is read out.The CPU 1 stores the video data in the memory 2. All you need to do is write the data and start address.

Figure 2(a) shows the memory (RAM) 2 in Figure 1.
FIG. 2(b) is a map of the management table in FIG. 2(a).

As shown in FIG. 2(a), the memory arrangement in the RAM 2 is such that a management table is specially provided at addresses A-B, and the other areas are basically used as video memory. a, b in Figure 2 (&).

c, (1, e is the start address of the video data for each line written by the CPU. a.

b, c, d, and e are the 1st raster and 2nd raster, respectively.

This is the start address of the Chang raster IA... and the CPU
2. As shown in FIG. 2(a), video data for each raster can be written to an arbitrary address.

As shown in FIG. 2(b), the starting address of each raster is written into the management table by the CPU.

In this way, since the first address for each address is managed, for example, soufflére can be performed from any position.

FIG. 3 is an operational flowchart of FIG. 1.

In the initial state, connection gates 3 and 4 connect CPU1 and R.
AM2 is both connected to a data bus and an address bus.

As a result, the CPU 1 writes video data to the RAM 2 (step 11). Of course, data for each raster can be written to a random address regardless of the order of the displayed rasters. Next, the CPU accesses the management table in the RAM 2 and writes the start address of each raster of the previously written video data (step 12).

Next, disconnect the CPUI from the main bus and
Pass the data onto the address bus (step 13).

That is, the address/data line of the CPU 1 is disconnected from the main bus according to the timing of al from the timing generator 5. Then, at the timing of a2, the management table address counter (ADC) 6
is connected to the address bus, and the first raster address shown in FIG. 2(b), that is, address A, is sent to RA, M2 via the address bus, and the shield/immediate table is accessed. Next, the data (video memory address a) in the address (address A) specified by the ADC 6 is read out, and the data is stored in the video memory address counter (VAC).
7 and at the same time increment ADC6 by 4.
- (step 14). Next, the value a set in VAC7 is counted, the RAM is accessed via the address bus, the video data in the address a specified by VAC7 is read out, and the video data in the address a specified by VAC7 is read out.
/S) Set to 8 and at the same time increment VAC7 (step 15). Next, the main bus is opened to the CPUI and at the same time video data from the P/S 8 is sent to the CRT (step 16). As a result, 1 rask N of video data is displayed on the CRT screen. Also, CPU1 only needs to include v5,
Since there is no intervention during reading, gates 3 and
4 connects the CPUI and RAM2 to the main bus and executes other processing. In this case, it is assumed that the RAM 2 includes a program area or a work area in an area other than the video memory. The screen display for one raster is finished at 7L, but since the entire screen is not finished (step 17.18), it is decided to go to step 13 again, the CPU is disconnected from the main bus by 9JfJL, and A
Connect DC6 to the address bus. In this way,
The incremented count value of ADC6 (1°2.
3...n rasters O) are sequentially sent to the management table via the address bus, and the contents (
a, b, c, d,...) and VA
Repeat the operation of setting C7. Then, the ADC 6 is incremented at timing a2 every time the raster ends, and returns to the initial state at timing a3 at the end of the n raster (step 22). Therefore, the ADC 6 is initially reset to the lowest address in the management table (that is, the A address of the l-th raster).

On the other hand, according to the timing of VAClj:sa4, the seventh count counted the video data address a issued from RAM2 and sent it to the address bus. lU
, a5 is incremented. V
A C711: , thus sequentially video data addresses a, b on the tube J'1 table.

c, d, . . . are set and sent to the AT1/S bus to output video data for each raster.

3jF, P/S 8 bi, video data for each raster is set at timing a5, and this is transmitted from the CRTD at timing a7.

Note that when the n-th raster video data is sent to the CRT,
When one screen is finished, check if there is a screen change (! (step 19)), if there is a screen change,
After the UI writes the changed data to RAM2 again, 'j
j The start address for each raster of the management table is used (step 20.21).

In the 70-chart of FIG. 3, the CPU 1 intervenes only in steps 11.12 and 20.21, and the other parts are performed by hardware and must be performed within the raster return time. This makes it possible to speed up and simplify processing.

In addition, since information can be changed for each raster, it is possible to subdivide the divided scroll (split scrolling can be done in blocks of up to two lines), set any line spacing, and move blocks within the display screen. etc., greatly expanding screen control functions.

Effects As explained above, according to the present invention, a CP that rewrites two counters and an e h:x table for each raster.
Since the RAM is accessed in a time-sharing manner with U, the processing of CPU (la) for display control is simplified and efficiency is improved, and the display control speed is increased and fine details on the display screen are You will be in charge.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a CRT display control device showing an embodiment of the present invention, and FIG. 2 shows a memory and ♀! FIG. 3 is a flowchart of the operation of FIG. 1. 1: CPTJ, 2: RAM, 3, 4: Gate, 5: Timing generator, 6: Counter (AD
C), 7: Counter ('VAC), 8: Noku parallel serial converter. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] G.) In a CRT display control device equipped with a video memory into which video data is written by the CPU, data is stored in a predetermined area of the video memory, and the video memory start address for each rask of the CRT is It has a management table registered for a plurality of rusks, a counter that increments and instructs the address of the management table, and a counter that increments and instructs the address of the upper video memory, and the above two counters A CRT display control device patented in which the video memory is accessed in a time-sharing manner by changing the contents of a management table in rows 50PU.