JPS59218772A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which can be readily positioned at masks, and has small collector-base junction capacity and low noise by simultaneously forming an emitter diffusing window and a base contacting window, and forming a base contacting high density layer with an emitter diffusing SiO2 as an ion implantation mask. CONSTITUTION:After an SiO2 film 6 is covered on a P type base region 4 coated with an Si3N4 film 5, and an emitter window 7 and a base window 8 are simultaneously opened by a photoetching method at the film 6. Then, with the film 6 as a mask, the film 5 is etched with thermal phosphoric acid to form an emitter window 7 and a base contacting window 8, and the film 6 is then removed. Subsequently, after an Si polycrystalline layer 9 which contains P, As is formed entirely, and SiO2 film 10 is covered on the film 5. Then, the film 10 is removed except the degree for covering the vicinity of the emitter window, and the layer 9 is removed except the vicinity of the emitter with the film 10 as a mask. Then, the impurity is diffused from the layer 9 by heat treatment to form an emitter region 11, a P type impurity ions are then shallowly implanted through the film 5, thereby forming a high density base region 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, particularly a super high frequency low noise transistor.

In conventional low-noise transistors, in order to reduce thermal noise due to base resistance, an emitter 103 and a base are formed by diffusion in a substrate 120 as shown in FIG. The emitter 103 and the base contact 101 are brought close together to narrow the active region 102 and reduce the base resistance. Base electrode 113. Emitter electrode 112
The contact holes were formed in the insulation 119 by vapor deposition of aluminum. However, in order to form the highly doped base contact region 101, the collector base junction must be several times deeper than the collector base junction of the active base region 102 due to the manufacturing process, which increases the collector base junction capacitance and increases the Gains were decreasing. Furthermore, it is extremely difficult to bring the emitter base contacts close to each other due to mask alignment, making it impossible to reduce the base resistance and making it impossible to reduce the noise based on this base resistance.

SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a transistor with a small collector-base junction and low noise.

According to the present invention, after forming the base region, silicon dioxide,
1. Temporarily cure the silicon nitride layer, provide an emitter window and a base contact window at the same time on the silicon oxide layer, break impurity-doped polycrystalline silicon or impurity-doped silicon dioxide near the emitter window, form an emitter by heat treatment, and then By implanting ions into the external base region through the TERRA silicon film, mask alignment between the adjacent emitter region and base region is facilitated, and noise is reduced by reducing the base resistance. The scale, and even the collector base junction: The reduction in u'ja results in good electrical characteristics in the high frequency band.

The present invention will be described below based on embodiments of NPN transistors.

As shown in FIG. 2(a), a silicon dioxide film 19 is formed on an N-type silicon epitaxial layer (20) having a desired thickness and specific resistance, and the silicon dioxide film 19 is coated with a photolithography method. The base diffusion window is Mfx, and a pP type base region 4 is formed by following it by thermal diffusion or ion implantation. Next, as shown in FIG.
(,10A) fc3-7L, silicon dioxide 6'r: is deposited thereon by vapor phase growth, and then an emitter window 7 is formed on this silicon dioxide film 6 by photolithography.
and the base window 8 are opened at the same time. Next, as shown in FIG. 2C, using the aforementioned silicon dioxide film 6 as a mask, the TERRA silicon film 5 is etched with hot phosphorus to form an emitter window 7 and a base contact window 8, and then a second process is performed. The silicon oxide film 6 is removed using hydrofluoric acid. Next.

As shown in FIG. 4(d), a polycrystalline silicon layer 9 containing a desired amount of arsenic or arsenic is formed over the entire surface to a desired thickness (for example, 2 UOOA) using a vapor phase growth method or the like. . - Silicon dibaride film 10 made by post-vapor growth method on the right
is deposited on the TERRA silicon film 5 by about 1.5 to 2 times. Furthermore, as shown in FIG. 2(e), the silicon dioxide film 10 is removed by photoetching, leaving just enough to cover the vicinity of the emitter window, and then the silicon polycrystalline layer 9 is removed using the silicon dioxide film 10 as a mask. Remove it leaving the area near the emitter. Next, as shown in the same figure (f),
An emitter region 11 is formed by diffusing impurities from the impurity-containing polycrystalline silicon layer 9 through heat treatment, and then P-type impurity ions are shallowly implanted through the silicon nitride film 5fc to form a highly concentrated base region 1. do. In this case, since the silicon dioxide film 1o is approximately 1.5 to 2 times as thick as the silicon nitride film 5, the acceleration energy can be selected so that ions do not reach the silicon polycrystalline layer 9. be. Then, activation heat treatment of the implanted ions is performed. Finally, as shown in FIG. 6G, after the entire silicon dioxide film 10 is removed with hydrofluoric acid, extraction electrodes 12 and 13 are formed by partially removing the aluminum vapor layer and photoetching.

In the above structure, if there is a possibility that the silicon polycrystalline layer 9 and the base extraction electrode 13 come into contact with each other, the extraction electrode 12.
Using 13 as a mask, the portions of the silicon polycrystalline layer 9 protruding from the lead electrodes 12 and 13 are removed by plasma etching or the like.

Moreover, instead of the impurity-containing polycrystalline silicon 9, impurity-containing silicon dioxide may be used as the emitter diffusion source. In that case, the silicon dioxide (silicon dioxide) converter 10 becomes unnecessary.

According to the conventional manufacturing method, strict mask alignment was required for ivy diffusion i6, base contact window formation, and impurity diffusion, and these were required separately, but according to the present invention, mask alignment is performed as shown in FIG. The process shown in b) can be performed at once, and since both the emitter diffusion window and the base contact window are formed at the same time, there is no need to worry about misalignment.

Furthermore, as shown in FIG. 2(b), the high concentration layer for the base contact is formed using silicon dioxide 10 for emitter diffusion as an ion implantation mask, so that the high concentration base Ifli
1 can be brought closer to the emitter region 11, and thermal noise due to the base resistance can be reduced. Furthermore, by appropriately selecting the ion implantation energy during the formation of the base layer 1, the base layer 1 can be formed shallowly, and the collector base junction valley-S can be reduced to improve the gain in the high frequency band. It is Ding Noh.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional ultra-high frequency low-noise transistor, and FIG. 1... External high HIit degree base area, 2...
... External base region, 3 ... Active base region, 4 ... Base region, 5 ... Silicon dioxide film, 6 ... Silicon dioxide jL7 ...
. . . Emitter window, 8 . . . Base contact doper, 9 . . . Polycrystalline silicon layer, 10 . . .
2...Emitter extraction electrode, 13...
・Base extraction electrode. Joya of the drawing (no change in content) / Tsume Otsuzu Me Otsuzu Showa Year Month Date Commissioner of the Patent Office 1, Indication of the case 1988 Patent Application No. 11198
No. 2, Title of the invention Manufacturing process 3 of the Semiconductor Devices 1 Office, Relationship to the amended case Applicant 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative Tadahiro Sekimoto 4, Agent Person 5. Date of amendment order: May 29, 1980 (shipment date) Full text of specification 1 and drawings/'r Agent: Patent attorney Uchihara T.L. ＼、、No□／

Claims (1)

[Claims] A base region of another conductivity type is formed on a semiconductor substrate of one conductivity type, a first insulating layer is formed on this base region, and an emitter diffusion window and a base contact g are simultaneously formed in this first insulating layer. , an impurity-containing layer having a second insulating layer using a different etchant from the first insulating layer is formed on the upper surface of the emitter diffusion window, and impurities are diffused from the impurity-containing layer into the base region. 1. A method for manufacturing a semiconductor device, comprising: forming an emitter region; forming a base electrode in contact with the base region at the base contact window; and an emitter electrode in contact with the impurity-containing layer.