JPS59212905A - Control system of programmable controller - Google Patents

Abstract

PURPOSE:To prevent the increment of the processing cycle by processing a sequence program after dividing said program into three levels in accordance with the processing speed. CONSTITUTION:A sequence program is divided into three levels, that is, the 1st level for processing at a high speed, the 2nd level for processing at a comparatively high speed and the 3rd level for processing at a comparatively low speed respectively. The program of the 1st level is processed for every cycle tau, and the program of the 2nd level is processed for every several cycles. The program of the 3rd level is processed in a period excepting the processing periods of the 1st and 2nd level programs. In such a way of processing, the increment of the processing cycle can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention and Prior Art The present invention relates to a control system for a programmable controller.

The programmable controller (hereinafter referred to as PC) is
An iterative calculation method is adopted in which processing is performed by repeating a sequence program, and it is desired that the cycle number for processing one sequence program be as short as possible. However, as the uses of PCs have expanded, the size of sequence programs has become larger, and therefore the processing cycle has become longer, which has become a problem. Therefore, in the past, sequence programs that had to be processed at high speed (hereinafter referred to as Tsutsu Lebel programs) and other sequence programs (hereinafter referred to as second level programs) were processed separately. For example, as shown in Figure 1,
Lebel's program has a constant period τ (e.g. 8III
SeC), and the second level program was divided appropriately and processed once in several cycles (in the example shown in Figure 1, it was divided into four parts, and the second level program was processed once in several cycles). (The two-level program is processed once.) and,
This process was repeated. 7J\However, the number of applications per month has further expanded, and programs that do not require special processing speed, such as programs that display various displays on a CRT screen and self-diagnosis programs, have to be processed as second-level programs. As a result, the size of the second level program becomes large, resulting in a problem that the processing cycle of the second level program, which should originally be processed quickly, becomes long.

OBJECT OF THE INVENTION The object of the present invention is to provide, among the above-mentioned second level programs,
The purpose of this invention is to separate programs that do not require relatively high speed as third-level programs to prevent an increase in the processing cycle of second-level programs.

Structure and operation of the invention As shown in FIG. 2, the present invention provides a first level program that requires high-speed processing to perform processing in each cycle, and then a second-level program that requires high-speed processing. The program is processed once for several rounds, and in the remaining time other than the processing time of the 2nd level program, the 3rd level program is executed during the time that was conventionally used as idling poetry.
That is, large programs such as operator message display and self-diagnosis that do not require speed are processed asynchronously.

Embodiment FIG. 3 is a block diagram of a PC. The PCI is used only when creating a sequence controller main body 101 and a sequence program, and is used only when creating a sequence program.
It has a programmer 102 that converts programs into machine language, modifies sequence programs, and the like.

102a is a keyboard used when creating a sequence program, and 102b is a random access memory (RAM) that stores the sequence program. 102C is a table that stores the correspondence between each piece of functional information designated by the operand of the sequence program and the storage location of the data memory 101a. 102
d is a read-only memory (ROM) that stores a control program that is controlled by the entire programmer 102, a language translation program that translates sequence programs input from the keyboard 102a into machine language, and the like. 10
2e has a processing unit (CPU) that executes translation, modification, etc. of the sequence program according to the program stored in the ROM 102d, and 102f has a buffer etc. that exchanges data with the sequence controller main body 101. The transmitter/receiver section 102g is a bus line.

101a is a data memory, 101b is a programmer 1
A transmitting/receiving unit 1010 having a buffer 7 and the like that controls data transfer between the programmer 102 and the RAM 1 which stores sequence programs translated into machine language.
101d is a ROM that stores a control program for controlling the sequence controller 101; 101c is a RAM for performing arithmetic processing; 101f is a processing device that stores a control program and performs predetermined sequence processing according to the sequence program; 1,101h is an input circuit and an output circuit for connecting with external equipment.

In the above configuration, when creating a sequence program, first, from the keyboard 102a, each function to be instructed by the sequence program and the data memory 101a are
102C and stores it in the table 102C, and then the first . Second. The sequence program of the third level is inputted from the keyboard 102a as shown in FIG. 4 by instructing each level, second level, and third level, and is stored in the RAM 102b.

Once these correspondence tables and sequence programs are stored, the language processing program stored in the ROM 102d is started and each instruction of the sequence program is transferred to the RAM.
From 102c, the calling instruction code and operand are sequentially converted into machine language.

Further, at the end of the second level, a jump instruction to the second level is attached, and furthermore, the second level program is appropriately divided and a division code is attached. Note that the operand is converted into machine language representing a predetermined location and a predetermined bit in the data memory 101a using a correspondence table. These sequence programs converted into machine language are sent to the programmer 10.
The data is transferred and stored in the RAM 101C via the transmitting/receiving section 102f of No. 2 and the transmitting/receiving section 101b of the sequence controller.

Thus, the first. Second. Each third level program is
This program and ROM are stored in the RAM 101c.
The processing device 101f performs sequence processing according to the control program stored in the control program 101d, and the program execution flow at this time is processed according to the flow shown in FIG.

That is, the sequence controller normally processes a third-level program, and is triggered from the third level to the third-level program by the interrupt request signal INT issued from the tarok timer at a constant period τ (8 m5ec in the above example). Jump to the level program, save the contents of the register during the third level program processing, and execute the level level program. When the program processing of this second level is completed, the program jumps to the second level by the second level jump command (2) added by the programmer 102, and processes the second level program. Then, in the middle of processing the second level program, the programmer 1
When the division code 0 added by 02 is read, (
Divided code is made up of call instructions, and a program called by the call instruction of divided code does not perform a normal return and return to the next part of the divided code, but returns to the end of the next label. Save it for the jump destination. ) The registers are restored, and the next return instruction (2) returns to the third level interrupt position, from which the third level program processing is performed again. Then, when the next interrupt request signal is output from the clock timer, the program jumps again to the program of the second level, processes the program of the second level as before, and then continues processing of the program of the second level.

In this way, the program processing of the level 2 is performed once every fixed period τ, and the program of the 2nd level is appropriately divided by the programmer 102 and processed once in several cycles (4 cycles in this embodiment). Process and repeat. The third level program is the first level program described above. Processing is performed using the time remaining in the second level program processing, and when the processing is completed, processing is performed again from the beginning. In this way, processing is performed at the timing shown in FIG.

Effects of the Invention The present invention compares a sequence program processed by a programmable controller (PC) with a second-level program that requires high-speed processing and a second-level program that requires high processing speed. It is divided into 3rd level programs that do not require high processing speed.The 3rd level program processes once every fixed cycle, the 2nd level program processes once every several cycles, and the 3rd level program processes the above 1st level program. The time remaining after the second level program processing is used to complete the first step. Three ranks of processing speeds are provided so that the processing is asynchronous with the second level program processing, so the processing speed of the sequence program can be changed depending on the purpose and nature of the sequence program, which increases the number of sequence programs. Therefore, programs that do not particularly require high processing speed will not slow down the processing speed of other programs.

[Brief explanation of drawings]

FIG. 1 is a conventional control method for a programmable controller, FIG. 2 is an example of a control method for a programmable controller according to the present invention, FIG. 3 is a hardware block diagram of an embodiment of the present invention, and FIG. This figure is a configuration diagram of an input program, and FIG. 5 is a flowchart of a control method according to an embodiment of the present invention. 1...Programmable controller, 101...
Sequence controller, 102...programmer,
102, a--keyboard, 101b, 102f, .
, transmitting and receiving section. Patent applicant Noanack Co., Ltd. (and 1 other person) Figure 1 Figure 2 Figure 4 Figure 3 01

Claims (1)

[Claims] The sequence program is divided into a first-level program that processes at high speed, a second-level program that requires processing speed, and a third-level program that does not require special processing speed. The program is processed every fixed cycle, the second level program is processed once every several cycles, and the third level program is processed using the time remaining from the above second level program processing within a fixed cycle. A control method for a programmable controller that performs