JPS5843770B2 - Asynchronous processing method for external devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an asynchronous processing method for external devices connected via an asynchronous interface, and more particularly to a different speed memory control method for a microprogram controlled central processing unit.

Generally, when controlling an external device connected via an asynchronous interface, especially a different speed memory, from a central processing unit, after the central processing unit accesses the memory device, the processing is temporarily suspended, and the operation is performed from the accessed memory device. A method is adopted in which processing is restarted when a completion signal or an operation completion notice signal is returned.

Here, the operation completion signal is returned at the access time of the memory device, and the operation completion notice signal is returned approximately one machine cycle of the central processing unit before the operation completion signal.

By the way, most central processing units are realized by microprogram control, and suspending the processing of the central processing unit is almost equivalent to suspending the execution of microinstructions, and restarting is equivalent to canceling the suspension of microinstruction execution.

In the conventional asynchronous processing method, the above-mentioned restart point is limited to either the time of receiving the operation completion signal or the time of receiving the operation completion notice signal.

As a result, restarting only when an operation completion signal is received reduces the processing capacity of the central processing unit, and restarting only when an operation completion notice signal is received increases the number of microinstruction words.

The present invention solves the above-mentioned drawbacks by providing a means that can selectively control restarting when an operation completion warning signal is received and restarting when an operation completion notice signal is received, thereby improving the processing capacity of the central processing unit and reducing the number of microinstruction words. The object of the present invention is to provide an asynchronous processing method for external devices that is achieved at the same time.

To achieve the above object, the present invention provides an information processing system in which a central control device and an external device are connected via an asynchronous interface, in which the external device responds to access from the central control device by sending a first response signal and The central control unit has a means for generating a second response signal delayed by a predetermined time from the first response signal, and the central control device has a means for generating a second response signal that is delayed by a predetermined time from the first response signal, and the central control device also has a means for generating a second response signal that is delayed by a predetermined time from the first response signal, and the central control device also has a second response signal for temporarily interrupting the processing after accessing the column device. a second means for restarting the processing upon receiving the first response signal from the external device; and a third means for restarting the processing after a predetermined time delay after receiving the first response signal. and a fourth means for selecting and specifying one of the second and third means.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sequence diagram illustrating asynchronous processing at the microinstruction step level, where a and b show an operational image according to the conventional method, and C shows an operational image according to the present invention.

The horizontal axis shows the flow of time, and each division represents one machine cycle.

In FIG. 1a, 4 means execution of a microinstruction,
A memory access request 1 instructed by the microinstruction is issued to the memory device.

5 also means the execution of a microinstruction, but depending on the microprogram processing target, after a memory access request, the next microinstruction cannot be processed unless there is a response from the memory device, or the next microinstruction cannot be processed even before a response from the memory. Since there are cases where there is a process that can be executed, it is indicated by a broken line.

Currently, the central processing unit and memory device are connected through an asynchronous interface, so after executing 4 or 5 microinstructions, the central processing unit temporarily suspends processing until a response signal is returned from the memory device. There is a need to.

3 is an operation completion signal sent back from the memory, and upon reception, the suspended microinstruction 6 resumes its processing execution.

In FIG. 1, 2 is an operation completion notification signal sent back from the memory, and upon receiving 2, the microinstruction 7 resumes processing execution.

Microinstruction 7 is used for processing such as updating the memory address register, which is allowed to be updated when there is a response from the memory device, and has a large effect on improving processing speed compared to Figure 1a. There is.

However, in general, in dynamic steps of a microprogram, type b processing occurs very frequently during memory access, but in static steps, type a processing occurs frequently.

Conventionally, the microinstruction restart method is fixed to either type a or type b, and if method a is adopted,
Although the number of microinstruction words can be reduced, the processing speed will decrease.If method b is adopted, the address for the next instruction etc. can already be calculated, and the processing speed will improve, but the number of invalid microinstructions will increase. The drawback is that the number of microinstruction words required increases.

FIG. 1C is a diagram showing a processing form according to the present invention, which incorporates the advantages of a and b.

That is, a means 8 is introduced which switches between a processing mode in which the microinstruction 6 is restarted by receiving the operation completion signal 3 and a processing mode in which the microinstruction 7 is restarted by receiving the operation completion notice signal 2. By enabling switching control according to the processing mode mentioned above during memory access, it is possible to simultaneously improve processing speed and reduce the number of micro hoods.

FIG. 2 is a block diagram showing one embodiment of the present invention, in which a memory device 10 and a central processing unit 20 are connected through an asynchronous interface.

When the memory device 10 receives a memory access request 31 from the central processing unit 20, the timing circuit 11 sends fi
The M'lE completion notification signal 32 and the operation completion signal 33 are returned after a predetermined time, respectively.

The operation completion notice signal 32 and the operation completion signal 33 are received by receiving circuits 22 and 23, respectively, and their outputs are input to a restart mode switching circuit 24, and further, this output is input to a microinstruction execution interruption control circuit 25.

A memory access request 31 is also input to the microinstruction execution interruption control circuit 25, and when this request is made, the execution of the next microinstruction is interrupted, and the output of the restart mode switching circuit 24 is energized. Cancels the suspension and resumes processing execution.

FIG. 3 is a block diagram showing in detail the restart mode switching circuit 24 and microinstruction execution interruption control circuit 25 of FIG. 2.

Reference numeral 40 denotes a microinstruction execution interruption control flip-flop, which is set by a memory access request signal 41.

When the flip-flop 40 is set, it instructs the microinstruction execution control unit 70 to suspend execution.

There are various methods for interrupting the execution of microinstructions, such as stopping the clock and changing the operation code portion of the microinstruction to a specific code, and the present invention may be adopted in any of these methods.

50 is a restart mode switching flip-flop, and when the flip-flop 50 is set by the signal line 51, the AND-OR circuit 60 is energized by the signal line 62, which is energized when the operation completion notification signal is received, and the flip-flop 40 is reset. .

When the flip-flop 40 is reset, the interrupt instruction for the microinstruction is released and execution resumes.

When the flip-flop 50 is reset in step 52, the same operation as described above is performed by the signal line 63 which is activated when the operation completion signal is received.

Note that 63 may be generated within the central control unit by delaying 62 by a predetermined time.

As explained above, the present invention introduces a restart method that can specify both the time of receiving an operation completion notice signal and the time of receiving an operation completion signal as a restart method after accessing a terminal device connected by an asynchronous interface. This has the effect of simultaneously increasing the processing speed of the central processing unit and reducing the number of microinstruction words.

[Brief explanation of drawings]

FIG. 1 is a sequence showing the point at which microinstruction execution is suspended and restarted, a and b are the conventional method, and C is the method according to the present invention. FIG. 2 is a block diagram showing an embodiment of the present invention. Figure 3 shows the restart mode switching circuit 2 in Figure 2.
FIG. 4 is a detailed block diagram of a microinstruction execution interruption control circuit 25; 1...Memory access request, 2...Operation completion notice signal, 3...Operation completion signal, 4, 5
, 6.7... Micro instructions, 10...
Memory device, 11... Timing circuit, 20.
... Central processing unit, 24 ... Resume mode switching circuit, 25 ... Micro instruction execution interruption control circuit, 31 ... Memory access request, 32 ...
. . . Operation completion notice signal, 33 . . . Operation completion signal, 40 . . . Microinstruction execution interruption control flip-flop, 50 . ...Microinstruction execution control unit.

Claims (1)

[Claims] 1. In an information processing system in which a central control device and an external device are connected via an asynchronous interface, the external device responds to an access from the central control device by receiving a first response signal and a signal predetermined from the first response signal. means for generating a second response signal with a time delay, and the central control unit includes first means for temporarily suspending processing after access to the column device; a second means for restarting the process upon receiving the response signal; a third means for restarting the process after a predetermined time delay after receiving the first response signal; and the second and third means. and a fourth means for selecting and specifying one of them.