JPS59198727A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS59198727A
JPS59198727A JP7479483A JP7479483A JPS59198727A JP S59198727 A JPS59198727 A JP S59198727A JP 7479483 A JP7479483 A JP 7479483A JP 7479483 A JP7479483 A JP 7479483A JP S59198727 A JPS59198727 A JP S59198727A
Authority
JP
Japan
Prior art keywords
pellet
base plate
semiconductor
metal base
silver paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7479483A
Other languages
English (en)
Inventor
Kimio Miyoshi
三好 君雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP7479483A priority Critical patent/JPS59198727A/ja
Publication of JPS59198727A publication Critical patent/JPS59198727A/ja
Pending legal-status Critical Current

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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/321Disposition
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/732Location after the connecting process
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    • H01L2224/8319Arrangement of the layer connectors prior to mounting
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    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 イ、産業上の利用分野 この発明は半導体装置の半導体ペレットマウント工程に
おける製造方法で、特に半導体ペレットを金属基板上に
導電性ペーストを使ってマウントする製造方法に関する
口、従来技術 トランジスタ等の半導体装置の一般例を第1図に示すと
、(1)は放熱板を兼ねる金属基板、(2)は金属基板
(1)上に半田(3)で電気的機械的に固着(マウント
)した半導体ペレット、(4)は金属基板(1)の近傍
から外方に延びる外部リード部材、(5)は半導体ペレ
ット(2)の表面電極と外部リード部材(4)に両端が
超音波ボンディングや熱圧着ボンディングで電気的機械
的に固定されたアルミニウム線等のワイヤ、(6)は要
部にモールド成形されて内部を気密封止す゛る外装樹脂
材である。
金属基板(1)は放熱板を兼ねるため熱伝導性の良好な
銅や銅合金系金属が使用されるが、半田(3)を用いた
ペレットマウント時に表面が酸化してペレットマウント
性が極度に損なわれるため、通常は金属基板(1)の全
面にニッケルメッキを施してから、特にペレットマウン
ト部誉にペレットマウント性を良好にする目的で金や銀
メッキを部分的に施している。また外部リード部材(4
)も銅や銅合金系金属が使用され、これも酸化防止にニ
ッケルメッキを全面に施してから特にワイヤボンディン
グ部分上にワイヤボンディング性を良好にする目的で金
や銀メッキを部分的に施している。ところが、上記ニッ
ケルメッキは全面メッキのため作業的に容易であるが、
金や銀メッキは部分メッキのためメッキの準備作業が大
変であり、且つ金や銀が高価なためメッキ費用が高価な
ものになる問題があった。
そこで最近は半田に代わり導電性ペーストを使って半導
体ペレットを金属基板にマウントする傾向にある。導電
性ペーストは銀や金などの金属粉とエポキシ樹脂等の熱
硬化性バインダと溶剤とを混練してペースト状にしたも
ので、これを金属基板上に定量塗布してからその上に半
導体ペレットを搭載して窒素雰囲気の加熱炉内で約35
0℃の温度で約30秒程度加熱して導電ペーストを硬化
させて半導体ペレットを金属基板上に電気的機械的に固
着する。
ハ1発明が解決しようとする問題点 しかし乍ら、このペレットマウント工程は窒素雰囲気に
保たれているものの、設備上の問題から半導体ペレット
の金属基板への供給時などに空気が巻き込まれるために
、完全な窒素雰囲気を保つことが困難になる。従って熱
処理時にメッキ処理をしていない金属基板や外部リード
部材はその表面が酸化されてペレットマウント性やワイ
ヤボンディング性を不安定ならしめる。特にパワー用の
半導体装置にあっては酸化層の介在によって熱抵抗特性
が損なわれ、半導体装置としての所定の特性が得られな
(なる。それ故に、金属基板の表面メッキを省略し得な
いのが現状である。
二4問題点を解決するための手段 本発明は導電性ペーストを使ったペレットマウント工程
における上記酸化上の問題点を解決することを目的とし
、これの達成手段として上述ペレットマウント工程にお
ける熱処理を低温低圧下で行うことを特徴とする。つま
り、本発明者は導電性ペーストを各種条件下で熱処理し
たところ、例えば大気圧により十分に低い数100mm
Hg以下の低圧雰囲気内で約100℃前後以下の温度で
熱処理すると従来の熱処理条件下と同様に導電性ペース
トを硬化処理できることを知見した。そこで本発明は金
属基板上に導電性ペーストを定量塗着し、その上に半導
体ペレットを搭載した後、全体を減圧下でかつ低温加熱
雰囲気内で熱処理してペレットマウントを行う方法を提
供する。この発明によれば金属基板や外部リード部材が
銅や銅合金系金属で構成され、かつその表面がメッキ処
理されていないものであっても、ペレットマウント時の
熱処理温度が低いので酸化される率が極端に少なくなり
、常に良好なペレットマウントや後のワイヤボンディン
グが実行される。
ホ、実施例 第2図乃至第4図から本発明の具体的実施例を説明する
。まず、第2図に示すように、表面に全くメッキ処理を
施していない厚さ2IIIIIIの銅製金属基板(7)
上に例えば85N量%の銀粉、エポキシ樹脂(バインダ
)、ブチルセルソルブ(溶剤)を混練してなる銀ペース
ト(9)を0.3rnB供給する。次に、第3図に示す
ように、金属基板(7)上の銀ペースト(9)に吸着コ
レラ) (10)で真空吸着された2mm角の半導体ペ
レット(8)を載せて左右方向にスクラブして銀ペース
ト(9)の半導体ペレット(8)下の厚さを約5μm程
度にする。然る後、第4図に示すように、真空度が約1
50mn+I1gで約70℃の温度雰囲気に保たれた低
圧加熱炉(11)内に入れ熱処理を行う、これにより銀
ペースト(9)は熱硬化され、半導体ペレット(8)は
金属基板(7)上に電気的機械的に十分良好に固着され
る。この時の金属基板(7)の表面酸化は皆無で、本発
明の有効性が認められた。
上記低圧加熱炉(11)内の圧力と温度は相対的な関係
にあって、例えば圧力を約100mm11gに下げ温度
を約100℃に上げても同様な結果が得られる。
へ9発明の効果 以上の如く、本発明によれば、ペレットマウント時にお
ける金属基板の酸化を実用上支障のない程度に抑えるこ
とができるので、半導体ペレットを金属基板に確実に固
着することができるし、特にパワー用の半導体装置にあ
っては熱抵抗特性を半田を用いるものと同程度に改善で
きる。また金属基板のベレットマウント部分に高価な部
分メッキを施す必要性が無くなるので、半導体装置のコ
ストを低減できる。
尚、本発明において、導電性ペーストはAgペーストに
のみ制約されないし、金属粉の占める割合も適宜に増減
できる。
【図面の簡単な説明】
第1図は一般的半導体装置の部分側面図、第2図乃至第
4図は本発明の詳細な説明するための半導体装置のベレ
ットマウント部分における部分側面図である。 (7)−−一金属基板、(8)−・半導体ペレット、(
9L−・導電性ペースト。

Claims (1)

    【特許請求の範囲】
  1. (11金属基板上に塗着した導電性ペースト上に半導体
    ペレットを搭載した後、減圧下でかつ低温加熱雰囲気内
    で熱処理することにより半導体ペレフトを金属基板上に
    電気的機械的に固着することを特徴とする半導体装置の
    製造方法。。
JP7479483A 1983-04-26 1983-04-26 半導体装置の製造方法 Pending JPS59198727A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7479483A JPS59198727A (ja) 1983-04-26 1983-04-26 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7479483A JPS59198727A (ja) 1983-04-26 1983-04-26 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS59198727A true JPS59198727A (ja) 1984-11-10

Family

ID=13557559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7479483A Pending JPS59198727A (ja) 1983-04-26 1983-04-26 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS59198727A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0330341A (ja) * 1989-06-28 1991-02-08 Mitsubishi Electric Corp 半導体装置の製造方法及びその装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53109477A (en) * 1977-03-07 1978-09-25 Toshiba Corp Mounting method of semiconductor element
JPS5575226A (en) * 1978-12-04 1980-06-06 Toshiba Corp Manufacturing semiconductor device
JPS5617029A (en) * 1979-07-20 1981-02-18 Toshiba Corp Installation of semiconductor pellet

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53109477A (en) * 1977-03-07 1978-09-25 Toshiba Corp Mounting method of semiconductor element
JPS5575226A (en) * 1978-12-04 1980-06-06 Toshiba Corp Manufacturing semiconductor device
JPS5617029A (en) * 1979-07-20 1981-02-18 Toshiba Corp Installation of semiconductor pellet

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0330341A (ja) * 1989-06-28 1991-02-08 Mitsubishi Electric Corp 半導体装置の製造方法及びその装置

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