JPS59197173A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a high speed IGFET by a method wherein an inverted trapezoidal recessed groove is provided on the surface of a semiconductor substrate surrounded by an oxide film, a gate electrode is buried in said groove through the intermediary of a gate oxide film, the gap located between the gate electrode and the recessed groove is filled up using an oxide film, and a source and drain region is formed in the substrate using said electrode as a mask, thereby enabling to prevent the overlapping of the gate electrode and the source and drain region. CONSTITUTION:A thick field oxide film 12 is formed on the circumferential part of a P type Si substrate 11, a thin oxide film 13 is coated on the substrate 11 surrounded by the field oxide film 12, an aperture is provided, and a concaved groove 15 having the inverted trapezoidal cross-section is formed on a channel region. Then, the film 13 is removed, a gate electrode 17 consisting of polycrystalline Si is buried in the groove 15 through the intermediary of a gate oxide film 16, and an oxide film 18 is filled up in the gap between the electrode and the groove. Subsequently, N<+> type source and drain regions 19 and 20 are formed in the substrate 11 using the electrode 17 as a mask, and both ends of the source and drain regions 19 and 20 are advanced to the point located below the films 12 and 18 by performing an activating process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical division of the invention] The present invention relates to a semiconductor device, and particularly to an insulating dart type field effect semiconductor device and a manufacturing method thereof.

[Technical background of the invention]

There has been remarkable progress in increasing the degree of integration of semiconductor devices, and in particular, in insulated gate type field effect semiconductor devices, elements have been significantly miniaturized as the degree of integration increases. For example, in the MO8 type L'SI, which is currently the focus of development, the effective channel length of the MOS transistor is already in the submicron range. Also, the current VLS I
The effective channel length of the MOS (MOS) transistors is also less than 2 μm, and is 1.7 to 1.5 μm. With such miniaturization, many problems have arisen that need to be solved, such as the occurrence of short channel effects and the problem of reduced reliability due to hot electrons.

The short channel effect is a phenomenon in which as the distance between the source and drain becomes shorter, the depletion layer due to the drain voltage approaches the source region, the surface potential of the channel decreases, and the threshold voltage (Vth) decreases. the result,
Controllability of the drain current due to the dart voltage deteriorates, and fluctuations in Vth increase, resulting in a significant deterioration of device performance. Furthermore, as the drain depletion layer approaches the source region, the electric field strength increases significantly in the channel region near the drain.

As a result, the generation of hot electrons due to the drain current and the generation of electron-hole pairs due to injected ionization become significant, leading to an increase in dirt flow and substrate irradiation. Further, hot electrons trapped in the dirt oxide film cause Vth to change over time, resulting in a decrease in reliability.

Therefore, in order to prevent the above-mentioned short channel effect and the problems associated with it, conventional
) have been adopted or proposed. In these figures, 1 is a silicon substrate, 2.2' is a source region, 3.3' is a drain region, 4 is a dirt oxide film,
5 is a dart electrode.

In the structure of FIG. 1(A), the diffusion depth of the source and drain regions 2 and 3 is made shallow in the vicinity of the dirt electrode 5, so that the source and drain regions 2.
This suppresses formation by penetrating downward, thereby suppressing shortening of the effective channel length.

That is, since the impurity diffusion for forming the source and drain regions 2 and 3 is isodirectional, the deeper the diffusion depth, the greater the penetration under the dirt electrode 5, and the closer the source and drain regions 2 and 3 are. It will be formed as follows. As a result, the effective channel length becomes shorter than the designed value, making short channel effects more likely to occur. On the other hand, according to the structure shown in FIG. 1(6), the source and drain regions 21 in the vicinity of the dirt electrode 1,
Since the diffusion depth of 3/ is shallow, it is possible to suppress the dirt from entering under the electrode 1, and there is a deep diffusion depth part 2 on the outside of the dirt electrode 1.
3, it is possible to avoid an extreme increase in series resistance that would occur if the overall diffusion depth was made shallow.

FIG. 1B shows a structure generally called a concave MO8, in which a concave groove deeper than the source and drain regions 2.3 is formed in the channel region. By providing this groove, a channel region is partially formed on the side wall of the groove, and a curved channel surface is formed as a whole. Therefore, if the effective channel length is the same, the circuit density can be increased compared to the conventional MOS, and the short channel effect can be suppressed.

[Problems with background technology]

However, the structure shown in FIG. 1(A) or FIG. 1(B) has the following problems.

First, in the structure shown in FIG. 1(A), there is a problem in that the shallow diffusion depth parts 2/ and 3/ of the source and drain regions inevitably have high resistance, reducing mutual conductance (gm) and making it difficult for current to flow. Ta. However, when the channel length is further shortened, there is a problem in that the regions 2 and 3 of the source and drain regions with large diffusion depths approach each other, making it easy to cause punch-through. Furthermore, the source and drain region portions 2 near the gate electrode 5
Although the diffusion depths of ' and 3' are shallow, it is not possible to completely prevent the source and drain regions 2' and 3' from penetrating below both ends of the gate electrode 5. Therefore, the gate electrode 5 and the source and drain region 2/
, 3/ occurs, which hinders improvement in switching speed.On the other hand, in the concave MO8 structure shown in FIG. 1(B), the concave MO8 structure shown in FIG.
The problem of a decrease in gm as in the case of the above does not occur, and even if the channel length is further shortened, a decrease in the Noyanchi-through breakdown voltage is unlikely to occur. However, in the case of concave MO8, MO
S) Let's cancel out the short channel effect by bending the channel surface, which has the most important effect on the characteristics of the transistor, and using the development effect (reverse short channel effect), which is completely opposite to the normal short channel effect of increasing the VTR caused by this. Therefore, there was a problem with the reliability of its characteristics.

That is, since the reverse short channel itself is caused by various factors, it is difficult to control its magnitude.
Balancing this further with short channel effects is extremely difficult.

In addition, the concave MO8 is a conventional M with a flat channel surface.
Since the manufacturing processes that have been accumulated for O8 type semiconductor devices cannot be applied, there is a problem in that the techniques that have been accumulated so far cannot be applied as they are to improve the reliability of the characteristics.

In addition, in the case of 4 MO8, as shown in FIG. 1(B), the overlap between the gate mh5 and the source and drain regions 2 and 3 must be large, and the problem of reduced switching speed due to parasitic capacitance is This appears much more prominently than the structure shown in FIG. 1 (5).

The main reason for this is that the source and drain regions 2 and 3 are not formed in self-alignment with the dart electrode 5, as described below.

That is, in the conventional manufacturing method of the concave 1Iv10S, as shown in FIG. 2(4)(B), for example, an n-type epitaxial layer 6 is grown on a p-type silicon substrate 1 (
Subsequently, by forming a groove 7 deeper than the epitaxial layer N6, source and drain regions 2 and 3 separated from each other in the channel region are formed. (Illustrated in FIG. 2(B)). After this state is achieved, a dirt oxide film 4 and a gate electrode 5 are formed, as shown in FIG.
Obtain the structure of B). In this case, iJ? of the dirt electrode 5? When turning, a margin is required for mask alignment to avoid so-called offset, so it is inevitable that the dirt electrode 5 will largely overlap the source and drain regions 2 and 3. .

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and uses a structure different from the conventional one to substantially reduce the diffusion depth of the source and drain regions without increasing resistance, thereby preventing short channel effects and punching. The present invention provides a highly reliable semiconductor device that can improve the through voltage and achieve excellent high-speed characteristics by suppressing overlap between the dirt electrode and the source and drain regions as much as possible, and a method for manufacturing the same.

[Summary of the invention]

A semiconductor device according to the present invention includes a -conductivity type semiconductor substrate;
a groove formed in the semiconductor substrate and having an inverted trapezoidal cross section;
a dirt electrode formed on the groove bottom of the groove via a dirt insulating film at a distance from the inclined opposing sidewall of the groove; and a dirt electrode filled between each sidewall of the groove and the dirt electrode. A formed insulating layer having a triangular cross section, a source region and a drain region having a conductivity type different from that of the substrate, which are provided on both sides of the groove and separated from each other, and these source and drain regions. It is characterized by comprising a channel region sandwiched therebetween and formed only under the bottom of the groove.

In the semiconductor device of the present invention, most of the source and drain regions are formed above the channel surface, that is, on the dart electrode side, so that the source and drain regions can be substantially reduced in thickness without reducing the thickness of the source and drain regions themselves. The same effect as when the diffusion depth is made extremely shallow can be obtained. Therefore,
Encroachment of the source and drain regions under the dirt electrode can be suppressed without reducing gm, reducing the short channel effect and A? Can prevent a drop in lentil pressure resistance.

By the way, the groove in the semiconductor device of the present invention is for increasing the diffusion length of the source and drain regions on the dirt m pole side than the channel surface level.
It is not intended to increase the effective channel length by using the inclined surface of the groove in a part of the channel region as in O8.

Therefore, the channel surface is flat like the conventional MO8 type semiconductor device, and there is no problem of the reverse short channel effect caused by bending the channel surface as in the concave MO8. It is possible to apply the technology that has been accumulated regarding type semiconductor devices. Therefore, extremely high reliability can be obtained compared to the concave MO8.

Furthermore, as described below, by applying the manufacturing method of the present invention, it is possible to prevent offset of the gate electrode.
When patterning the dirt electrode, a mask alignment margin is not required so much. Therefore, the overlap between the gate electrode and the source and drain electrodes is significantly smaller than in the concave MO8K, reducing parasitic capacitance and improving switching speed.

Next, an outline of the method for manufacturing a semiconductor device according to the present invention will be explained.

One manufacturing method according to the present invention includes the steps of: - forming a groove having an inverted trapezoidal cross section in a planned channel region of a conductive type semiconductor substrate; and sequentially forming a dart insulating film and a dart electrode material layer on the substrate. forming a gate electrode spaced apart from the inclined opposite sidewall of the groove at the bottom of the groove via a dirt insulating film by patterning the laminated layers; Filling the gap with the inner wall of the groove with an insulating material layer and flattening a region extending from the surface of the insulating material layer to the surface of the substrate; The method is characterized by comprising a step of forming source and drain regions separated from each other up to the ends of the dirt electrodes by doping using the electrodes as a mask.

A second manufacturing method according to the present invention includes the steps of forming a semiconductor substrate of one conductivity type having a reverse conductivity type semiconductor layer on the surface layer, and having a cross-sectional shape of an inverted trapezoid in a planned channel region and deeper than the opposite conductivity type semiconductor layer. forming a source and drain region separated by the groove by forming a groove;
After f-) an insulating film and a dirt electrode material layer are sequentially laminated on the substrate, this is layered with 1? A step of forming a dirt electrode spaced apart from the inclined opposite sidewall of the groove through a dirt insulating film at the bottom of the groove by turning, and controlling diffusion of impurities from the source and drain regions. Accordingly, the method is characterized by comprising a step of forming source and drain regions up to below the ends of the gate electrodes.

According to the first or second manufacturing method according to the present invention, the diffusion length below the channel surface level is suppressed as much as possible, and offset of the gate electrode is prevented, and the semiconductor according to the present invention has the characteristic structure described above. The device can be manufactured. In particular, the first manufacturing method has the advantage that the source and drain regions can be formed on the dirt electrode by oneself, similar to the normal polycrystalline silicon dating process.

[Embodiments of the invention]

Examples of the semiconductor device and the manufacturing method thereof according to the present invention will be described below. Example 1 (FIG. 3 (6) to G) ) The surface is selectively oxidized to form a field oxide film 12, and a thermal oxide film 13 is formed on the surface of the device region surrounded by the field oxide film 12.Subsequently, an opening is formed in the intended channel region. A resist pattern 14 is formed (as shown in FIG. 3).

(ii) Next, the thermal oxide film 13 is selectively etched using the resist pattern 14 as a mask to expose the substrate surface in the area where the channel region is to be formed, and then the resist pattern 14 is removed (31d (B)). ).

(iii) Next, using the thermal oxide film 13 as a mask, the silicon substrate 11 is selectively etched with KOH to form a groove 15 with an inverted trapezoidal cross section in the intended channel region (as shown in FIG. 3(C)). ).

Gv) Next, after removing the thermal oxide film 13, the surface of the element region is thermally oxidized to form a dirt oxide film 16 on the entire surface, and a polycrystalline silicon layer is further deposited thereon by the CVD method. Subsequently, the polycrystalline silicon layer and the date oxide film were formed using A? photolithography. By turning, the groove 1
A dart electrode 17 is formed on the bottom surface of 5 (FIG. 3(D)).
(Illustrated).

At this time, the dirt electrode 17 is formed so as not to protrude from the bottom surface of the groove, that is, so as not to overlap the inclined side wall of the groove 15. Therefore, for the turning, it is desirable to use reactive ion etching (=XE) which has excellent microfabrication properties.

(V) Next, a silicon oxide film 18 is formed on the entire surface by CVD method.
After depositing the silicon oxide film 18, the unnecessary portions are removed by etching, thereby forming the silicon oxide film 18 only in the gap between the recesses 15.
The surface of the silicon oxide film 180 is planarized to cover the entire device region (as shown in FIG. 3(G)).

(vD) Next, phosphorus is ion-implanted using the gate electrode 17, silicon oxide film 18 and field oxide film 12 as a blocking mask, and then the implanted phosphorus is activated to form male-type source and drain regions 19. 20 is formed by self-alignment (as shown in FIG. 3(F)).

The depth of phosphorus ion implantation at this time can be controlled by the accelerating surface pressure. Therefore, if the amount of phosphorus seeped out in the subsequent thermal process is calculated and the ions are implanted into a part slightly shallower than the bottom of the groove 15, the source and drain regions 19 and 20 will be formed under the end of the dirt electrode 17 in the final process. It is possible to completely prevent off-set by reaching this point, and to minimize the overlap with the dart electrode 17.

Note that if the silicon oxide film 18 is not present at this time,
Source and drain regions 19 near dirt electrode 17
．． The diffusion depth of 20 becomes extremely large, and the effect of the present invention cannot be obtained.

(vii) Next, the entire surface of the interlayer insulating film is coated with CvD-8i.
After depositing the O2 film 21 and opening a contact hole,
The source electrode 22. is formed by vapor deposition and turning of aluminum. Aluminum wiring such as the drain electrode 23 is formed to obtain the MO8 type semiconductor device shown in FIG. 3(G).

The manufacturing method of the above embodiment can be carried out by applying the conventional polycrystalline silicon dirt process almost as is, except for the formation of the groove 15 and the formation of the silicon oxide film 18.

Example 2 (FIG. 4 (4) to F) (1) First, a layered epitaxial silicon layer 32 is grown on a p-type silicon substrate 31 (as shown in FIG. 4 (5)).
.

Note that the n-type layer 32 may be formed by diffusing an n-type impurity such as phosphorus into the surface of the p-type silicon substrate 31.

(11) Next, by selectively performing anisotropic etching with KOH to form a groove 33 with an inverted trapezoidal cross section deeper than the n-type epitaxial silicon ff'132 in the intended channel region and the intended field part. , n-type source and drain regions 34 and 35 are formed (as shown in FIG. 4B).

(iii) Next, by selectively oxidizing the field region, a field oxide film 36 is formed to isolate each element region (as shown in FIG. 4(C)).

Up to this stage, the manufacturing process of the conventional concave MO8 is substantially the same.

0) Next, after forming a dirt oxide film 37 by thermally oxidizing the surface of the purple region, a gate vH pole 38 is formed on the bottom surface of the groove 33 by depositing and turning a polycrystalline silicon layer. (Illustrated in Figure 4).

At this time as well, the dirt electrode 38 is connected to the groove 3 as in the first embodiment.
Form it so that it does not cover the side wall of 3. Therefore, the dirt electrode 38 necessarily forms the source and drain region 34.3.
5, which results in an offset, which is different from the manufacturing method for the concave MO8.

Incidentally, unnecessary portions of the dirt oxide film 37 may be removed in the same manner as in the first embodiment.

(V) Next, the n-type impurities in the source and drain regions 34' and 35 are exuded downward through a heat treatment process, and the diffusion depth of the source and drain regions 34' and 35 is made slightly deeper than the channel surface.・Resolve the set state (as shown in Figure 4 (G)).

At this time, seepage of impurities is controlled so that the overlap between the source and drain regions 34 and 35 and the ff pole does not become too large.

(After that, in the same manner as in Example 1, the AA wiring 40 is formed by depositing an interlayer insulating film 39, forming a contact hole, depositing aluminum, and patterning. get.

Note that in this embodiment, the source and drain regions 34.
35 is not formed by self-alignment.

Therefore, the dart electrode 38 may be formed using gold L4 such as aluminum by performing the processes shown in FIG. 4(D) and later using a conventional aluminum dart process.

As shown in FIG. 5, the MO8 type semiconductor devices manufactured in the above-mentioned Examples 1 and 2 each have a characteristic structure according to the present invention, thereby producing effects unique to the present invention. That is, if the source and drain regions 19.20 are cut at the channel surface level as shown by the broken line in the figure, the portion below the broken line is the source and drain region 19.2.
This is a normal MO8 structure with extremely shallow 0. and,
Since the source and drain regions 19 and 20 are formed thickly in the portion above the broken line, the portion below the broken line can be made as thin as possible without considering an increase in sheet resistance. Therefore, the depth of penetration into the bottom of the gate layer becomes significantly smaller, the short channel effect is significantly suppressed, and the parasitic capacitance is also reduced when compared with the conventional structure shown in FIG. 1(A). Further, in the case of FIG. 1A, there was a problem of a decrease in punch-through breakdown voltage between the source and drain portions 2 and 3 having deep diffusion depths, but this problem can also be prevented in the semiconductor device of the above embodiment. In addition, the source and drain regions 19 and 20 as a whole have a sufficient diffusion depth, so that no special low-temperature diffusion is required.
It has the advantage that the source and drain regions 19, 20 with substantially shallow junctions can be formed by a normal thermal process.

On the other hand, unlike the concave MO8 structure, the semiconductor device of the above embodiment has a flat channel surface, so that the problem of reduced reliability peculiar to the concave MO8 caused by the curved channel surface does not occur. Furthermore, as is clear from the description of the above embodiments, unlike in conventional concave MOSs, the dirt electrodes do not overlap greatly over the source and drain regions, so parasitic capacitance is significantly reduced and switching speed is improved. be able to.

Note that in the semiconductor device of the above embodiment, f of the dart electrode 17 is
A parasitic capacitance will occur between the f111 plane and the sloped surfaces of the source and drain regions 19.20, but this capacitance is not large enough to affect the switching speed. That is, since the end faces of the source and h''ray regions 19 and 2o are inclined, the distance between them and the side surface of the gate electrode 17 is large. Since the above-mentioned parasitic capacitance can be further reduced by slanting the side surface of the dart electrode 17 in the opposite direction, the capacitance during this period does not pose much of a problem in terms of characteristics.

〔Effect of the invention〕

As detailed above, according to the present invention, a structure is provided in which the diffusion depth of the source and drain regions can be made substantially shallow and the overlap with the gate electrode can be suppressed as much as possible without increasing the series resistance. As a result, it is possible to provide a high-speed and highly reliable semiconductor device and its manufacturing method that can solve various problems such as the short channel effect that occur with miniaturization of elements.

[Brief explanation of drawings]

Figures 1 (4) and (B) are cross-sectional views showing the structure of an MO8 type semiconductor device that has been proposed in the past for the purpose of preventing the short channel effect, and Figures 2 (A) and (B) are Figures 1 ( B) is a cross-sectional view for explaining the manufacturing method of the MO8 type semiconductor device having the structure, and FIGS. 4(5) to C) are sectional views sequentially showing the manufacturing process according to another embodiment of the present invention, and FIG. 5 is a sectional view shown in FIGS. FIG. 6 is an explanatory diagram of the operation and effect of the MO8 type semiconductor device obtained in (G) to (F), and FIG. 6 is an explanatory diagram showing another embodiment of the semiconductor device according to the present invention. 11.31...p-type silicon substrate, 12.36...
Field oxide film, 13... Thermal oxide film, 14... Rennost pattern, 15.33... Concave] J 15
. 37... Dirt oxide film, 17.38... Dirt electrode, 18... Silicon oxide film, 19.34... Source region, 20.35... Drain region, 21.39...
- Interlayer insulating film, 22, 23.40... aluminum wiring. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 4 Figure 4 Figure 5

Claims (5)

[Claims] (1) - An m-type semiconductor substrate, a groove formed in the semiconductor substrate and having an inverted trapezoidal cross section, and a dart at the bottom of the groove spaced apart from the slanted opposing sidewall of the groove. A gate electrode formed through an insulating film, an insulating layer having a pentagonal cross section filled between each side wall of the groove and the dirt electrode, and an insulating layer having a pentagonal cross section formed on both sides of the groove. A source region and a drain region each having a conductivity type different from that of the substrate are provided separately, and a channel region is sandwiched between the source region and the drain region and formed only under the full width of the groove. A semiconductor device characterized by: (2) The semiconductor device according to item (1) of the patent application, wherein the dart electrode is formed to have a trapezoidal cross section. (3)-A step of forming a groove having an inverted trapezoidal cross section in the intended channel region of a conductive semiconductor substrate, and after sequentially laminating a goot insulating film and a dirt electrode material layer on the substrate. By patterning, a gate M! is formed at the bottom of the groove. (3) completely forming a dirt electrode separated from the inclined opposite side wall of the groove via an edge film; filling the gap between the pole side end and the inner wall of the groove with an insulating layer; By flattening the region extending from the surface of the material layer to the surface of the substrate, and doping the substrate with impurities of opposite conductivity type using the dirt electrode as a mask, the mutual contact between the ends of the dirt electrode is 1. A method of manufacturing a semiconductor device, comprising the step of forming separate source and drain regions. (4) The method for manufacturing a semiconductor device according to claim (3), wherein a polycrystalline silicon layer is used as the dirt electrode material layer. (5) Forming a single-conductivity heavy type semiconductor substrate having a reverse conductivity type semiconductor layer on the surface layer, and forming a groove having an inverted trapezoidal cross section and deeper than the reverse conductivity type semiconductor layer in a portion where a channel region is to be formed. A step of forming source and drain regions separated by the recess ri4, and sequentially forming a gate insulating film and a dirt electrode material layer on the substrate A'7, and then patterning them. r of the groove
The dirt electrode is formed by forming a dirt electrode on the bottom of K via a dirt insulating film, and forming a dirt electrode spaced apart from the inclined opposing sidewall of the four concave grooves, and by controlling the diffusion of impurities from the source and drain regions. 1. A method of manufacturing a semiconductor device, comprising the step of forming source and drain regions up to the bottom of the end.