JPS5919487B2 - analog to digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter with high speed and high resolution.

With recent advances in microcomputers (MPUs), attempts are being made to replace various analog systems with digital systems.

In this case, it is necessary to convert the analog signal into a digital signal, but the resolution associated with this A/D conversion directly affects the accuracy, continuity, etc. of the digital system.

For this reason, how to perform high-resolution A/D conversion is a major problem in improving the precision and continuity of digital systems.

In order to increase the resolution of A/D conversion, it is possible to use a counting type A/D converter or a high resolution A/D converter.

However, the former has the disadvantage of slow conversion speed, and the latter has the disadvantage of being complex and expensive.

Here, the present invention aims to realize an A/D converter with high resolution using a simple circuit configuration.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 10 is a comparator to which an analog signal e1 is applied to one input terminal, and 20 is a processor which receives the signal from the comparator 10 as an input, for example, a microcomputer is used for this.

30 is a D/A converter that converts the digital signal from the processor 20 into an analog signal; 40 is connected to the output side of the D/A converter and converts the digital signal from the processor 20 into an analog signal;
This is a dither signal generation circuit that generates a dither signal by changing the output of the A converter in a stepwise manner. It consists of a switch S.

The comparator 10 compares the analog signal e1 applied to one input terminal with the signal e1 from the dither signal generation circuit 40 applied to the other input terminal, and inputs the comparison result to the processor 20. It is given as a signal.

The processor 20 has at least a successive approximation function and a counting function, and has an input port 21, a data memory section 22 composed of read/write memory, for example, and an arithmetic control section 23.
, for example, a program memory section 24 composed of a read-only memory and an output port 25.

The input port 21 receives the signal from the comparator 10 and waits for the output signal of the comparator 10 to be read by the signal from the arithmetic control section 23.

The data memory section 22 temporarily stores a signal applied from the input port 21, for example, according to a signal from the calculation control section 23, and stores calculation results.

The program memory unit 24 stores in advance conversion procedures for converting input analog signals into digital signals, data necessary for calculations, etc., and the contents thereof are stored in the calculation control unit 2.
It is read out by the signal from 3.

The arithmetic control section 23 reads the state of the signal given to the human power port 21, writes it to the data memory section 22, decodes the conversion procedure and arithmetic procedure from the program memory section 24, and reads it from there. Digital operations are performed using data and signals read from the data memory section 22.

The output port 25 is supplied with a digital signal output from the data memory section 22 or the arithmetic control section 23, and is connected to the D/A converter 30 by the signal from the arithmetic control section 23.
A digital signal or a control signal is output to the dither signal generation circuit 40.

The D/A converter 30 converts the digital signal output from the output port 25 into an analog signal, and supplies this to the other input terminal of the comparator 10 via the dither signal generating circuit 40.

In the present invention, a dither signal is generated using a step output from a D/A converter, and is a temporarily delayed signal, a sawtooth wave signal, or a triangular wave signal that continuously increases and/or decreases over time. collectively, and
The amplitude value (final value) is the ILS of the D/A converter 30.
B (Le a s t 51gn1f1cantB
It corresponds to an integer multiple of it).

The device configured as described above operates in that it first performs an N-width conversion operation using a successive approximation method without generating a dither signal, and then performs an A/D conversion operation using a counting method with a dither signal generated. It has the characteristics of

The operation will be explained in detail below with reference to the flowchart shown in FIG.

First, the apparatus is placed in a mode (successive approximation mode) in which an A/D conversion operation is performed using a successive approximation method.

In this successive approximation mode, the processor 20 turns on the switch S of the dither signal generation circuit 40 and controls the dither signal generation circuit 40 so as not to generate a dither signal. , input analog signal e1 is converted to 1 by successive approximation method.
Convert to digital signal.

That is, initially, N formed in a part of the calculation control section 23
Set the topmost digit of the register, pit 1'' (step ■).

This gives 50% of the total capacity of the N register to the N register.
A digital quantity corresponding to the value is set.

Next, the contents of the N register are output to the D/A converter 30 (
Step ■).

As a result, the D/Ai converter 30 converts the digital quantity corresponding to the 50th factor into an analog quantity, and this analog signal e is applied to the other input terminal of the comparator 10.

Next, the output signal of the comparator 10 is read and the state of the signal is determined (step 2).

Here, the state of the read signal is "0", that is, e,
(If it is e, reset "1", which was initially set in the most significant bit of the N register, to "par 0" (step 2).

Also, the state of the read signal is 1″, that is, el>el
If so, at 1 n set in the most significant bit of the N register is left unchanged.

Next, determine whether or not this person's register has completed all digits (step ゛■). If not, for the next digit, that is, the most significant bit, the second bit (1/2 for the most significant bit) (with a weight of 2) is set to °゛1'' (step).

As a result, the content of the N register (a digital signal corresponding to the 25th or 75th column of the total capacity) is set.

Here, the procedure returns to step (2) again, and operations in steps (2) to (2) are performed in the same manner as described above.

Now, in step ■, the third bit is "l".
is set.

In this way, the operations of steps 1 to 2 are continued until all the digits in the N register are completed, that is, until tt 1 n or "0" is set in the least significant bit of the N register.

Then, when all the digits are completed, the successive approximation mode ends,
The content D1 left in the N register is the value obtained by converting the input analog signal e1 into a digital signal using the successive approximation method, and its resolution corresponds to the number of bits of the D/A converter 30.

Subsequently, the device shifts to a mode (counting mode) in which A/D conversion operation is performed using a counting method.

In this counting mode, the processor 20 first resets the contents of a counting counter formed in a part of the arithmetic control section 23 (step 2).

Also, the switch S of the dither signal generation circuit 40 is turned off, and the output signal of the D/A converter 30 is transferred to this D/A converter 30.
For example I LSB' (LeastSignif
icant Bit) in a stepwise manner (step ■).

As a result, the output of the D/A converter 30 changes as shown in FIG.
As shown at the beginning of FIG. 3, f is a time constant of a resistor 41 and a capacitor 42, and becomes a dither signal with an amplitude IL8B that increases with time toward the output signal of the D/A converter.

Subsequently, the processor 20 reads the output signal of the comparator 10 and determines the state of the signal (step '■).

The state of the signal read here is par 0'', that is, el
>ef, add 1 to the counting counter (step D).

Thereafter, until the state of the output signal of the comparator 10 becomes 1",
That is, step 1 is repeated until the input analog signal e1 and the signal ef from the dither signal generation circuit 40 match.
and repeat step °C.

Then, when e1≦ef, the counting mode ends, and the content D2 remaining on the counter becomes t (
This value corresponds to e (the position of the input analog signal e1 within the ILSB).

These relationships are expressed by the following equation.

IOgeXoctxocD2 Therefore, by adding the digital signal D1 obtained in the successive approximation mode and the digital signal D2 obtained in the counting mode as shown in FIG. A high-resolution digital signal corresponding to the analog signal e1 can be obtained.

According to such a device, in the successive approximation mode, the input analog signal e1 is converted at high speed into the digital signal D1 having the number of bits equal to the number of bits of the D/A converter 30, and the range of ILSB is converted in the counting mode. As a whole, high-speed and high-resolution A/D conversion can be performed.

Furthermore, since it is composed of a comparator, a processor, a D/A converter, and a dither signal generation circuit, the overall configuration is simple.

Furthermore, since the dither signal generation circuit is connected to the output side of the D/A converter 30 and the dither signal is obtained by changing the output signal of the D/A converter in steps,
The amplitude value (final value) of the dither signal is always transferred to the D/A converter 30.
Since the dither signal can be made an integer multiple of ILSB, no conversion error occurs due to the amplitude value of the dither signal being not constant.

FIG. 5 is a block diagram showing another embodiment of the present invention.

In this embodiment, comparators 10 and 11 each having an input analog signal e1 as one input are provided on the input side of the processor 20, and the output terminal of the D/A converter 30 is connected to the other input terminal of the comparator 10. However, the output terminal of the dither signal generation circuit 40 is connected to the other input terminal of the comparator 11.

By reading the output signal of the comparator 11, the function of the switch S in FIG. 1 is provided.

That is, in the successive approximation mode, the A/D
Perform the conversion at high speed and in counting mode, comparator 1
1. A/D conversion is performed in a loop including the processor 20, the D/A converter 30, and the dither signal generation circuit 40.

FIG. 6 is a flowchart in the case where the output of the D/A converter 30 is changed stepwise by, for example, 2 LSB between the positive polarity side and the negative polarity side in the counting mode, and FIG. 7 is an operation waveform diagram thereof.

In this case, a positive dither signal with an amplitude of 2LSB is generated according to the procedure from step ① to step [share], and the time ta from when the positive dither signal e is generated until el,1 matches the input analog signal e1 is Next, a negative polarity dither signal with an amplitude of 2 LSB is generated according to the procedure from step ① to step [phase], and the period from when the negative dither signal e f 2 is generated until ef 2 matches the input analog signal e 1 is calculated. Time fs'5: Find b.

Then, in step (2), by calculating 'ta+tb, the digital signal D2 in the counting mode is calculated.
I'm trying to get it.

According to such a procedure, as shown in FIG. 7, the dither signal obtained from the dither signal generation circuit 40 becomes a signal that changes almost linearly with time, and the slope angles θ of the positive and negative dither signals are both equal. .

Therefore, since ta+tb corresponds to ILSB a, the digital signal D2 corresponding to exta+tb (analog value from Dl to el) can be accurately obtained by calculating □.

According to such a procedure, the dither signal generation circuit 40
Even if the values of the circuit elements change, as long as the positive and negative dither signals are symmetrical, the accuracy of A/D conversion is not affected.

Moreover, the step change width of the output signal of the D/A converter is 2
Since the LSB is large, the comparison operation becomes reliable and the inclination angle θ of the dither signal becomes large, which increases the conversion speed in the counting mode.

FIG. 8 is a block diagram showing still another embodiment of the present invention.

In this embodiment, a current output type is used as the D/A converter 30, and the dither signal generation circuit 40
The amplifier 43 is constructed of a parallel circuit with a resistor 41 and a capacitor 42 connected between the input and output terminals of this amplifier.

Note that the switch S connected in series to the capacitor 42 is a switch that controls the timing of dither signal generation.

According to this device, the dither signal obtained from the dither signal generator 40 is a signal that changes linearly with time.

Note that the dither signal generation circuit may have any other circuit configuration as long as it utilizes the output signal from the D/A converter to generate the dither signal.

As explained above, according to the present invention, with a simple configuration,
A high-speed, high-resolution A/D converter can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is a flowchart showing -fu of the operation of the processor,
FIG. 3 is an explanatory diagram of the operation in the counting mode, FIG. 4 is a conceptual diagram of the converted digital signal, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. A flowchart for changing the output of the A converter in steps of 2 LSB to the positive and negative polarity sides, FIG. 7 is an operating waveform diagram, and FIG. 8 is a block diagram showing still another embodiment of the present invention. 10... Comparator, 20... Processor, 30... D/A converter, 40... Dither signal generation circuit.

Claims (1)

[Claims] 1. A comparator that receives a human analog signal as one input, a processor that receives the signal from the comparator and has at least a successive approximation function and a counting function, and converts the digital signal from the processor into an analog signal. A D/A converter that converts signals is connected to the output side of this D/A converter so that when a step-change signal is applied, it outputs a signal that continuously changes approximately linearly over time. The processor first stops the operation of the dither signal generating circuit, and forms a loop including the comparator, the processor, and the D/A converter, and the The input analog signal is converted into a digital signal using the successive approximation method, and then the D/
By changing the output of the A converter stepwise and operating the dither signal generation circuit, a dither signal that continuously changes from the output side of the dither signal generation circuit to the output signal of the D/A converter is generated. The digital signal corresponding to the input analog signal is calculated from the digital signal obtained by the successive approximation method and the digital signal corresponding to the counted value. An analog-to-digital converter characterized in that it operates to obtain a signal. 2. The analog-to-digital converter according to claim 1, which uses an integrating circuit of a resistor and a capacitor as the dither signal generating circuit. 3 A current output type is used as the D/A converter, and the dither signal generating circuit is constructed from an amplifier and a parallel connection circuit of a resistor and a capacitor connected between the input and output terminals of this amplifier. The analog-to-digital converter according to item 1. 4 The processor uses the successive approximation method to convert the input analog signal into 1
In the operation of converting to a digital signal, the output signal of the D/A converter is changed stepwise between the positive polarity side and the negative polarity side, and the time required for the dither signal to match the input analog signal is counted, and The analog-to-digital conversion according to claim 1, wherein a digital signal corresponding to the input analog signal is obtained from a digital signal obtained by calculating a count value and a digital signal obtained by a successive approximation method. vessel.