JPS59193016A - Method of producing laminated condenser - Google Patents

Method of producing laminated condenser

Info

Publication number
JPS59193016A
JPS59193016A JP6718583A JP6718583A JPS59193016A JP S59193016 A JPS59193016 A JP S59193016A JP 6718583 A JP6718583 A JP 6718583A JP 6718583 A JP6718583 A JP 6718583A JP S59193016 A JPS59193016 A JP S59193016A
Authority
JP
Japan
Prior art keywords
layer
multilayer capacitor
plating
terminal electrode
silicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6718583A
Other languages
Japanese (ja)
Inventor
晃 田中
河野 敏郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KCK CO Ltd
KEE SHII KEE KK
Original Assignee
KCK CO Ltd
KEE SHII KEE KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KCK CO Ltd, KEE SHII KEE KK filed Critical KCK CO Ltd
Priority to JP6718583A priority Critical patent/JPS59193016A/en
Publication of JPS59193016A publication Critical patent/JPS59193016A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (イン発明の技術分野 本発明は、留層コンデンサの製造ツノ法に関する。[Detailed description of the invention] (Technical field of invention The present invention relates to a horn method for manufacturing a retention layer capacitor.

(a)従来技術と問題点 従来、積層コンデンサは、端子電極としてAg/Pd金
属粒子と適当量のガラス質フリットを加えた電極ペース
トを塗布、焼付することにより製造されていた。しかし
、この方法ではl) d金属の酸化による半田付は性不
良を生じ、又半田付けにより端子電極が半Ill中に移
行(くわれ)し、端子電極が欠損する欠点があった。
(a) Prior Art and Problems Conventionally, multilayer capacitors have been manufactured by applying and baking an electrode paste containing Ag/Pd metal particles and an appropriate amount of glassy frit as terminal electrodes. However, this method has the disadvantage that soldering due to oxidation of the metal causes poor quality, and that the terminal electrode is transferred into the semicircle due to soldering, resulting in damage to the terminal electrode.

そこで、かかる欠点を改善するため、端子電極上にニッ
ケル層及び半田層(又はSn)をメッキ方法により設け
、半田付は性、半田くわれ性を改善する方法が提案され
ている。
In order to improve this drawback, a method has been proposed in which a nickel layer and a solder layer (or Sn) are provided on the terminal electrode by plating to improve solderability and solder breakage.

しかし乍ら、この方法はメッキ時に前記端子電極部の極
く微少なボイド(空隙)がらメッキ液が浸入し、電気的
特性(特にQイ1111)を劣化させる欠点があった。
However, this method has the disadvantage that during plating, the plating solution enters into the extremely small voids (gaps) in the terminal electrode portion, deteriorating the electrical characteristics (particularly Qi1111).

(ハ)発明の目的 本発明はかかる不都合を解消するために創案されたもの
であり、積層コンデンサの半田イ;]り性。
(c) Purpose of the Invention The present invention has been devised to eliminate such disadvantages, and is aimed at improving the solderability of multilayer capacitors.

半84 <われ性を改善するとともに高品質な債Jヒコ
ンデンサを製造することを目的とする。
The purpose of this project is to improve its characteristics and to manufacture high-quality bond capacitors.

仁)発明の構成 本発明は、この目的を達成するために、セラミック誘電
体内に内部電極を多数埋設し、側端部の内部電極がW6
出する面に端子電極を設iノた4・へ屓コンテンサの製
造ノコ法において、前記ケゼ;1子電極部にニッケル層
及び半田層を設けるに際し2、該端子電極部にシリコン
層を設ける構成とし7だ。
In order to achieve this object, the present invention has a large number of internal electrodes embedded in a ceramic dielectric, and the internal electrodes at the side ends are W6.
4. In the sawing method for manufacturing a capacitor in which a terminal electrode is provided on the surface to be exposed, 2) when providing a nickel layer and a solder layer on the single electrode portion, a silicon layer is provided on the terminal electrode portion. The composition is 7.

(ホ)発明の実施例 次に、本発明を図面に茫づいて説明する。(E) Examples of the invention Next, the present invention will be explained with reference to the drawings.

席法に従って、まず第1図のように、セラミック誘電体
2の内部に内部電極3を多1iづ埋設した積層セラミッ
ク素体]を作り、次に第2図のよ・うにこの積層セラミ
ック素体lの側端部の内H1;電極3が露出した端面1
a、laに耐メツキ用の端子電極5を設けた積層コンデ
ンサ素体4を作る。
According to the seat method, first, as shown in Fig. 1, a laminated ceramic element with internal electrodes 3 embedded in a ceramic dielectric 2 in multiples is made, and then this laminated ceramic element is made as shown in Fig. 2. H1 inside the side end of l; end surface 1 where electrode 3 is exposed
A multilayer capacitor element body 4 is prepared in which terminal electrodes 5 for plating resistance are provided at a and la.

次いで、このG’fl?ii:1ンデンサ素体4を例え
は1〜20%シリコン溶液に畳清し、例えば2〜]0分
間真空含浸させる。その後、この積層コンデンサ素体4
を取り出し、遠心脱水機に例えは20秒〜5分間かけて
余分なシリコンを取り除いた後、150〜250℃、1
時間で乾燥し、シリコンを硬化して第3図のように桔屓
コンテンサ素体4の端子電極部5にソリコン層7を設i
Jる。
Next, this G'fl? ii: The 1-densor element body 4 is soaked in, for example, a 1 to 20% silicone solution, and vacuum impregnated for, for example, 2 to 0 minutes. After that, this multilayer capacitor body 4
Take it out, use a centrifugal dehydrator for 20 seconds to 5 minutes to remove excess silicone, and then heat it at 150 to 250℃ for 1 hour.
After drying for a while and hardening the silicon, a silicon layer 7 is formed on the terminal electrode portion 5 of the capacitor element body 4 as shown in FIG.
Jru.

史に、第3図に示すMHコンデンサ素体6のシリコン層
7の端子電極5に相当する部(i’fにメッキ方法によ
りニッケル層9を第4図のように形成した後、このニッ
ケル層9上に更に第5図のように半1(((Pd Sn
) Ml Oを設&Jて本発明の積層コンデンサCとす
る。
In history, after forming a nickel layer 9 by a plating method on a portion (i'f) of the silicon layer 7 of the MH capacitor body 6 shown in FIG. 3 corresponding to the terminal electrode 5, as shown in FIG. Further on top of 9, half 1 (((Pd Sn
) MlO is set to form a multilayer capacitor C of the present invention.

ここて、ト記ニッケル屓9及び半田層10を形成するメ
ッキ方法の一例を説明する。
An example of a plating method for forming the nickel layer 9 and the solder layer 10 will now be described.

先ず、第3図に示す積層コンデンサ素体6をアルカリ脱
脂し、イオン交換水により洗滌を行ない、次に、表面活
性化の為の表面処理液に浸油し7、肉ひイオン交換水に
て洗滌する。次いで、ター−(通電媒体)と猜Hコンテ
ンサ素体6を混合し5、スルファミン酸ニッケルメッキ
液によりハレルメソキを行ない、第4図の禎屓コンデン
ザ素体8とする。次に、イオン交換水により洗滌を行な
い、半田メッキ浴により前記同様ハレルメノギ力法によ
り半田メッキを行なう。次いで、イオン交換水により洗
滌を行ない、再び乾燥及び熱処理を行なって第5図に示
す積層コンデンサCとする。
First, the multilayer capacitor body 6 shown in FIG. 3 was degreased with alkali and washed with ion-exchanged water. Next, it was immersed in oil in a surface treatment solution for surface activation, and then washed with ion-exchanged water. Wash. Next, the tar (current-carrying medium) and the capacitor element body 6 are mixed together and subjected to Haller's plating using a nickel sulfamate plating solution to form the condenser element body 8 shown in FIG. Next, washing is performed with ion-exchanged water, and solder plating is performed using a solder plating bath using the Hallel Menogi force method as described above. Next, the capacitor is washed with ion-exchanged water, dried and heat-treated again to form a multilayer capacitor C shown in FIG.

前記メッキ工程に於て、pH,/I!!度、液濃度。In the plating process, pH, /I! ! degree, liquid concentration.

時間、電圧、電流及び洗滌が管理ポイントであることは
云うまでもない。また、上記メッキ方法は一例であり、
これに限定されるものではない。
Needless to say, time, voltage, current, and cleaning are control points. In addition, the above plating method is an example,
It is not limited to this.

次に、本発明による実験結果を表に示す。Next, the experimental results according to the present invention are shown in the table.

中No、lは2125型Cに100))F及びN o 
Medium No, l is 2125 type C 100)) F and No
.

2は同型SF、470 P Fを使用し、Q値不良判定
はQイi*2000以上を良、2000未満を不良とし
た。また、従来方法とはシリコン層を設けないで、ニッ
ケル層、半田層をメッキ処理にて形成したものを云う。
2 used the same type SF, 470 PF, and the Q value was determined to be defective when Qi*2000 or more was considered good and less than 2000 was considered bad. Furthermore, the conventional method refers to a method in which a nickel layer and a solder layer are formed by plating without providing a silicon layer.

本発明においてシリコン層の形成は、端子電極部の微少
ボイドからのメッキ液浸人による電気特性(Q (A 
)の劣化を防止するのが主たる目的であるが、シリコン
層の形成が浸清力/l:によるためセラミック部を含む
全表面に形成される。しかし5、このシリコン層形成に
よりセラミ・ツク部へ障害を与えることはなく、端子電
極と同様の効果がセラミック部においても奏されている
ものと考えられる。
In the present invention, the electrical properties (Q (A
) The main purpose is to prevent the deterioration of the silicon layer, but since the silicon layer is formed based on the immersion force/l:, it is formed on the entire surface including the ceramic part. However, 5. the formation of this silicon layer does not cause any damage to the ceramic part, and it is thought that the same effect as that of the terminal electrode is exerted on the ceramic part as well.

(ト)発明の効果 上述のように本発明によれば、端子電極を設けた積層コ
ンデンサ素体に直接ニッケル層及び半田層を設りずに、
一旦シリコン圏を設りるため、ニッケル層及び半田層を
設りるためのメッキ工程で、メッキ液が端子電極部の極
く微少なボイドに浸透することがなくなり、メッキ処理
が(i(f実に行なえ、積層コンデンサの半131(N
jけ性、半田くわれ(11゛が改善され、電気的特性特
にQ値の劣化を防止できる。
(G) Effects of the Invention As described above, according to the present invention, without directly providing a nickel layer and a solder layer on a multilayer capacitor body provided with terminal electrodes,
Once the silicon sphere is provided, the plating solution will not penetrate into the extremely small voids in the terminal electrode part during the plating process for forming the nickel layer and the solder layer, and the plating process will be (i(f) Actually, half of the multilayer capacitor is 131 (N
Scratchability and solder cracking (11゛) are improved, and deterioration of electrical characteristics, especially Q value, can be prevented.

また、上記シリコン層がセラミック誘電体全面を被覆す
るため、セラミック誘電体の内部か確実に保護され、高
品質な積層コンデンサを得ることかできるなどの利点を
有する。
Further, since the silicon layer covers the entire surface of the ceramic dielectric, the inside of the ceramic dielectric is reliably protected, and a high-quality multilayer capacitor can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第11図カキ第5図は本発明の実施例に於ける製造上程
を示す断面図、第6図は第5図に於ける入部拡大断面図
である。 ■・・・積層コンデンサ素子、2・・・セラミック誘電
体、3・・・内部電極、4.6.8・・・積層コンデン
サ素体、5・・・端子電極、7・・・シリコン屓、9・
・・ニッケルILIO・・・半田層、C・・・M層コン
テンサ。 第1図 第5図 9 °/ 第2図 ] 14図 第6図 ワ
FIG. 5 is a cross-sectional view showing the manufacturing process in an embodiment of the present invention, and FIG. 6 is an enlarged cross-sectional view of the entrance in FIG. 5. ■... Multilayer capacitor element, 2... Ceramic dielectric, 3... Internal electrode, 4.6.8... Multilayer capacitor element, 5... Terminal electrode, 7... Silicon layer, 9・
...Nickel ILIO...solder layer, C...M layer capacitor. Figure 1 Figure 5 Figure 9 °/ Figure 2] Figure 14 Figure 6

Claims (1)

【特許請求の範囲】 (11セラミック誘電体内に内部電極を多数埋設し、側
端部の内部電極が露出する面に端子電極を設けた積層コ
ンデンサの製造方法において、前記端子電極部にニッケ
ル層及び半田層を設けるに際し、該端子電極部にシリコ
ン層を設げることを特徴とする積層コンデンサの製造方
法。 (2)  シリコン層がt+ ?N方法により設けられ
ることを特徴とする特許請求の範囲第1項記載の積層コ
ンデンサの製造方法。
[Scope of Claims] (11) A method for manufacturing a multilayer capacitor in which a large number of internal electrodes are buried in a ceramic dielectric and terminal electrodes are provided on the surfaces where the internal electrodes are exposed at the side ends, wherein the terminal electrode portions include a nickel layer and A method for manufacturing a multilayer capacitor, characterized in that when providing a solder layer, a silicon layer is provided on the terminal electrode portion. (2) Claims characterized in that the silicon layer is provided by a t+?N method. 2. The method for manufacturing a multilayer capacitor according to item 1.
JP6718583A 1983-04-16 1983-04-16 Method of producing laminated condenser Pending JPS59193016A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6718583A JPS59193016A (en) 1983-04-16 1983-04-16 Method of producing laminated condenser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6718583A JPS59193016A (en) 1983-04-16 1983-04-16 Method of producing laminated condenser

Publications (1)

Publication Number Publication Date
JPS59193016A true JPS59193016A (en) 1984-11-01

Family

ID=13337580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6718583A Pending JPS59193016A (en) 1983-04-16 1983-04-16 Method of producing laminated condenser

Country Status (1)

Country Link
JP (1) JPS59193016A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122104A (en) * 1985-11-20 1987-06-03 松下電器産業株式会社 Electrode treatment of laminated chip varistor
JP2014072516A (en) * 2012-09-27 2014-04-21 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122104A (en) * 1985-11-20 1987-06-03 松下電器産業株式会社 Electrode treatment of laminated chip varistor
JPH0727803B2 (en) * 1985-11-20 1995-03-29 松下電器産業株式会社 Electrode treatment method for laminated chip varistor
JP2014072516A (en) * 2012-09-27 2014-04-21 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component

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