JP2871716B2 - Method for manufacturing resin-molded semiconductor device - Google Patents
Method for manufacturing resin-molded semiconductor deviceInfo
- Publication number
- JP2871716B2 JP2871716B2 JP1097978A JP9797889A JP2871716B2 JP 2871716 B2 JP2871716 B2 JP 2871716B2 JP 1097978 A JP1097978 A JP 1097978A JP 9797889 A JP9797889 A JP 9797889A JP 2871716 B2 JP2871716 B2 JP 2871716B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- lead frame
- resin
- lead
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂モールド型半導体装置の製造方法に関
し、特に表面がCuを主体とする素材からなるリードフレ
ームを使用した樹脂モールド型半導体装置の製造方法に
関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a resin-molded semiconductor device, and more particularly to a method for manufacturing a resin-molded semiconductor device using a lead frame whose surface is mainly made of Cu. About the method.
〔従来の技術〕 従来、この種の樹脂モールド型半導体装置は、Cu又は
Cu合金からなるリードフレームを使用し、半導体素子を
Agペースト等を用いてリードフレームにマウントした
後、Agペーストをキュア（一般に150℃、２時間）し、
半導体素子をリードフレームに固着する。[Prior art] Conventionally, this type of resin-molded semiconductor device is Cu or
Using a lead frame made of Cu alloy,
After mounting on a lead frame using Ag paste etc., cure the Ag paste (generally at 150 ° C for 2 hours)
The semiconductor element is fixed to the lead frame.
その後、半導体素子の電極とリードフレームの内部リ
ードとを、Auワイヤ等によりボンディング接続（一般に
150〜350℃）する。更に、この半導体素子を保護し、且
つ外部導出リードを固定するために、樹脂モールド（一
般に150〜175℃）を行う。After that, the electrodes of the semiconductor element and the internal leads of the lead frame are bonded and connected by Au wire or the like (generally,
150-350 ° C). Further, in order to protect the semiconductor element and fix the external lead, resin molding (generally at 150 to 175 ° C.) is performed.
こうして組立てられた半導体装置は、組立工程（Agペ
ーストキュア工程，ワイヤボンディング工程，樹脂モー
ルド工程）中の加熱により、外部導出リードは酸化され
ている。そのため、一般に外部に導出したリード部に
は、電解半田めっき法又はディップ法によって半田めっ
きを施し、半導体装置が取り付けられる外部装置との電
気的接続の際に用いられる半田等の濡れ性を改善した構
造を有している。In the semiconductor device assembled in this manner, the external leads are oxidized by heating during the assembly process (Ag paste curing process, wire bonding process, resin molding process). Therefore, generally, the lead portion led out to the outside is subjected to solder plating by an electrolytic solder plating method or a dip method to improve wettability of solder and the like used for electrical connection with an external device to which a semiconductor device is attached. It has a structure.
そして、半田めっきを施した後、不要リードフレーム
部を切断加工し、外部導出リードを成形加工して半導体
装置は完成する。又、リードフレームはワイヤボンディ
ング性を良くするために、内部リードのワイヤ接続部に
部分Agめっきを施したものが一般に使用されている。Then, after the solder plating is performed, the unnecessary lead frame portion is cut, and the external lead is formed, whereby the semiconductor device is completed. Further, in order to improve the wire bonding property, a lead frame in which a wire connection portion of an internal lead is partially plated with Ag is generally used.
上述した従来の樹脂モールド型半導体装置の製造方法
は、樹脂モールド後、外装めっきを施すために組立工程
が複雑となり、コスト高となっていた。In the above-described conventional method of manufacturing a resin-molded semiconductor device, an outer plating is applied after resin molding, which complicates an assembly process and increases costs.
更に、電解半田めっき法では、通常、半田めっき液及
びその前処理工程での処理液に強酸溶液が使用され、半
導体装置はその強酸溶液中に長時間浸漬（15〜30分）さ
れる。Further, in the electrolytic solder plating method, a strong acid solution is generally used for a solder plating solution and a treatment solution in a pretreatment step, and a semiconductor device is immersed in the strong acid solution for a long time (15 to 30 minutes).
そのため、リードフレームとモールド樹脂との微小隙
間に強酸溶液が侵入し、樹脂モールド境界のリードフレ
ームに内部腐食が生じ易くなり、更に、侵入イオンの除
去が困難となって残留イオンによる半導体装置の使用条
件下における電解腐食が生じ易くなり、電気的オープン
不良が発生するという欠点を有していた。As a result, the strong acid solution intrudes into the minute gap between the lead frame and the mold resin, and the internal corrosion of the lead frame at the boundary of the resin mold is liable to occur. Under such conditions, electrolytic corrosion is apt to occur, and there is a drawback that an electrical open failure occurs.
又、ディップ法による半田めっきでは、半田めっき時
の温度が高い（250〜280℃）ために、半田ディップ時の
熱ストレスにより、リードフレームとモールド樹脂との
界面の隙間が大きくなり、プレッシャークッカーテスト
などの結果、耐湿性が原因で電気的絶縁性の劣化が生じ
易いといった欠点を有していた。Also, in the solder plating by the dip method, the temperature at the time of the solder plating is high (250 to 280 ° C), so the thermal stress at the time of the solder dip increases the gap between the interface between the lead frame and the mold resin, and the pressure cooker test As a result, there is a defect that electrical insulation is likely to deteriorate due to moisture resistance.
本発明の樹脂モールド型半導体装置の製造方法は、少
なくとも表面がCuを主体とする素材からなるリードフレ
ームを使用した樹脂モールド型半導体装置の製造方法に
おいて、樹脂モールド後、酸洗浄により表面の酸化膜を
除去し、さらに純水洗浄を施した後乾燥処理を行なうこ
とにより、外部導出リードの表面にリードフレーム素材
のCu面をそのまま露出させることを特徴としている。The method for manufacturing a resin-molded semiconductor device of the present invention is a method for manufacturing a resin-molded semiconductor device using a lead frame at least on the surface of which is mainly composed of Cu. By performing a drying process after removing pure water and further performing a pure water cleaning, the Cu surface of the lead frame material is directly exposed on the surface of the external lead-out lead.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を示す縦断面図であ
る。Cu又はCuを主成分とする素材からなるリードフレー
ム１は、ワイヤボンディング性を改善するための部分Ag
めっき２を内部リードに有している。このリードフレー
ム１上にAgペースト３を用いて半導体素子４をマウント
し、その後Agペースト３をキュア硬化させ、半導体素子
４を固着している。FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention. The lead frame 1 made of Cu or a material containing Cu as a main component has a portion Ag for improving the wire bonding property.
Plating 2 is provided on the inner lead. The semiconductor element 4 is mounted on the lead frame 1 using the Ag paste 3, and thereafter, the Ag paste 3 is cured by curing to fix the semiconductor element 4.
又、半導体素子４の電極部（図示せず）とリードフレ
ーム１の内部リード上の部分Agめっき２とを、Auワイヤ
５でボンディングしている。更に、半導体素子４等を保
護するために、エポキシ樹脂等のモールド樹脂６で封止
している。外部導出リード1aは、樹脂モールド後必要形
状に切断，成形されている。なお、外部導出リード1a
は、半田めっき等の被膜を施しておらず、リードフレー
ムの素材を露出させている。Further, an Au wire 5 bonds the electrode portion (not shown) of the semiconductor element 4 and the Ag plating 2 on the internal lead of the lead frame 1. Further, in order to protect the semiconductor element 4 and the like, it is sealed with a mold resin 6 such as an epoxy resin. The external lead 1a is cut and formed into a required shape after resin molding. In addition, externally derived lead 1a
Does not provide a coating such as solder plating and exposes the material of the lead frame.
次に、本発明の樹脂モールド型半導体装置の製造方法
について説明する。まず、半導体素子をCu又はCu合金か
らなるリードフレーム上にマウント固着した後、ワイヤ
ボンディングによって半導体素子の電極と内部リードと
を接続し、樹脂モールドを行う。Next, a method for manufacturing the resin mold type semiconductor device of the present invention will be described. First, after the semiconductor element is mounted and fixed on a lead frame made of Cu or Cu alloy, the electrodes of the semiconductor element and the internal leads are connected by wire bonding, and resin molding is performed.
しかる後に、一つの方法として５〜15wt％の塩酸又は
硫酸溶液中に30〜60秒浸漬し、樹脂モールドされていな
い部分のリードフレーム表面の酸化物を除去した後純水
洗浄し、その後80〜100℃のエアー中で３〜10分間乾燥
する。Thereafter, as one method, the substrate is immersed in a hydrochloric acid or sulfuric acid solution of 5 to 15 wt% for 30 to 60 seconds to remove oxide on the surface of the lead frame which is not resin-molded, and then washed with pure water. Dry in air at 100 ° C for 3-10 minutes.
又、別の方法としては、組立工程中で高温となる工
程、すなわち半導体素子マウント固着，ワイヤボンディ
ング，樹脂モールドの各工程で還元性雰囲気（例えばH2
を５〜10vol％含むN2ガス）を用いることにより、リー
ドフレーム表面の酸化を防止する方法でもよい。Further, as another method, a reducing atmosphere (for example, H 2) is used in the steps of raising the temperature in the assembling step, that is, in the steps of fixing the semiconductor element mount, wire bonding, and resin molding.
The use of N 2 gas) containing 5～10Vol% a, or a method of preventing oxidation of the lead frame surface.
こうして得られた半導体装置のリードフレームの不要
部分を最後に切断し、所定の必要形状に外部導出リード
を成形して半導体装置を完成する。Unnecessary portions of the lead frame of the semiconductor device thus obtained are finally cut, and external leads are formed into a predetermined required shape to complete the semiconductor device.
第２図は本発明の第２の実施例を示す縦断面図であ
る。リードフレーム７は、Fe又はFe−Ni合金などのFe系
合金９からなり、Cuめっきが施されている。又、ワイヤ
ボンディング性を改善するために、内部リードに部分Ag
めっき２が設けてある。FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention. The lead frame 7 is made of an Fe-based alloy 9 such as Fe or an Fe-Ni alloy, and is plated with Cu. Also, to improve the wire bonding property, use Ag
Plating 2 is provided.
このリードフレーム７上に、Agペースト３にて半導体
素子４を固着し、半導体素子４と内部リードの部分Agめ
っき２とをAuワイヤ５にてボンディング接続し、更にモ
ールド樹脂６を用いて封止している。The semiconductor element 4 is fixed on the lead frame 7 with the Ag paste 3, the semiconductor element 4 and the part Ag plating 2 of the internal lead are bonded and connected with the Au wire 5, and further sealed with the mold resin 6. doing.
外部導出リード7aは、第１の実施例と同様必要形状に
切断成形され、半田めっき等の被膜は施さず、リードフ
レーム素材のCuめっき部を露出させている。The external lead 7a is cut and formed into a required shape in the same manner as in the first embodiment, and a coating such as solder plating is not applied, and the Cu plating portion of the lead frame material is exposed.
なお、組立工程中で前述の還元性雰囲気を使わない場
合、Cuめっき８の厚さは0.4μｍ以上が好ましい。0.4μ
ｍ未満では、下地のFe又はFe系合金９が酸化し、外部装
置との接続に使用する半田の濡れ性を悪くすることがあ
る。When the above-mentioned reducing atmosphere is not used in the assembling process, the thickness of the Cu plating 8 is preferably 0.4 μm or more. 0.4μ
If it is less than m, the underlying Fe or Fe-based alloy 9 may be oxidized and the wettability of the solder used for connection with an external device may be deteriorated.
次に、第１表（次頁）に、従来の半導体装置と本発明
による半導体装置との、半田付け性及びプレッシャーク
ッカーテスト（PCT）による電気特性劣化の割合を、同
一形状，同一条件下で比較した結果を示す。Next, Table 1 (next page) shows the solderability of the conventional semiconductor device and the semiconductor device according to the present invention and the ratio of the deterioration of the electrical characteristics by the pressure cooker test (PCT) under the same shape and the same condition. The result of the comparison is shown.
第１表によれば、本発明の半導体装置は半田付け性で
は差はなく、耐湿性では改善されていることがわかる。 According to Table 1, it can be seen that the semiconductor device of the present invention has no difference in solderability and is improved in moisture resistance.
以上説明したように本発明は、外部導出リードに半田
めっき等の被膜を形成せず、リードフレームの素材であ
るCu又はCu系合金のままか、あるいはFe又はFe−Ni合金
に施したCuめっきをそのまま露出させている。従って、
加工工数が低減でき、低コストの半導体装置を提供でき
る。As described above, the present invention does not form a coating such as solder plating on the external lead, Cu or Cu-based alloy which is the material of the lead frame, or Cu plating applied to Fe or Fe-Ni alloy Is exposed as it is. Therefore,
The number of processing steps can be reduced, and a low-cost semiconductor device can be provided.
又、電解半田めっき処理のような長時間の酸浸漬や、
半田ディップ処理のような高温処理が樹脂モールド後不
要となり、耐湿性に優れた半導体装置を提供できる。Also, long-time acid immersion such as electrolytic solder plating,
High temperature treatment such as solder dipping is not required after resin molding, and a semiconductor device having excellent moisture resistance can be provided.
第１図は本発明の第１の実施例の縦断面図、第２図は本
発明の第２の実施例の縦断面図である。 １…リードフレーム、1a…外部導出リード、３…Agペー
スト、４…半導体素子、５…Auワイヤ、６…モールド樹
脂、７…リードフレーム、7a…外部導出リード、８…Cu
めっき、９…Fe又はFe系合金。FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, and FIG. 2 is a longitudinal sectional view of a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Lead frame, 1a ... External lead, 3 ... Ag paste, 4 ... Semiconductor element, 5 ... Au wire, 6 ... Mold resin, 7 ... Lead frame, 7a ... External lead, 8 ... Cu
Plating, 9 ... Fe or Fe-based alloy.
Claims (1)
なるリードフレームを使用した樹脂モールド型半導体装
置の製造方法において、樹脂モールド後、酸洗浄により
表面の酸化膜を除去し、さらに純水洗浄を施した後乾燥
処理を行なうことにより、外部導出リードの表面にリー
ドフレーム素材のCu面をそのまま露出させることを特徴
とする樹脂モールド型半導体装置の製造方法。In a method of manufacturing a resin-molded semiconductor device using a lead frame having at least a surface mainly composed of Cu, an oxide film on the surface is removed by acid cleaning after resin molding, and further purified water cleaning. A method of manufacturing a resin-molded semiconductor device, wherein a Cu surface of a lead frame material is exposed as it is on a surface of an external lead-out by performing a drying process after performing the process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1097978A JP2871716B2 (en) | 1989-04-17 | 1989-04-17 | Method for manufacturing resin-molded semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1097978A JP2871716B2 (en) | 1989-04-17 | 1989-04-17 | Method for manufacturing resin-molded semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02275659A JPH02275659A (en) | 1990-11-09 |
| JP2871716B2 true JP2871716B2 (en) | 1999-03-17 |
Family
ID=14206751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1097978A Expired - Fee Related JP2871716B2 (en) | 1989-04-17 | 1989-04-17 | Method for manufacturing resin-molded semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2871716B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2611146B2 (en) * | 1994-08-04 | 1997-05-21 | 楢本理化工業株式会社 | Drying method of semiconductor lead frame |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS633444A (en) * | 1986-06-24 | 1988-01-08 | Furukawa Electric Co Ltd:The | Semiconductor device |
-
1989
- 1989-04-17 JP JP1097978A patent/JP2871716B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02275659A (en) | 1990-11-09 |
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