JPS5969908A - Method of forming external electrode of chip type electronicpart - Google Patents

Method of forming external electrode of chip type electronicpart

Info

Publication number
JPS5969908A
JPS5969908A JP18174882A JP18174882A JPS5969908A JP S5969908 A JPS5969908 A JP S5969908A JP 18174882 A JP18174882 A JP 18174882A JP 18174882 A JP18174882 A JP 18174882A JP S5969908 A JPS5969908 A JP S5969908A
Authority
JP
Japan
Prior art keywords
electrode layer
electrode
plating
layer
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18174882A
Other languages
Japanese (ja)
Inventor
健治 大石
秀紀 倉光
黒田 孝之
隆 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP18174882A priority Critical patent/JPS5969908A/en
Publication of JPS5969908A publication Critical patent/JPS5969908A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電子部品のプリント配線基板等に使1  用
されるチ・プ形電子部品の外部電極形成方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming external electrodes of chip-shaped electronic components used in printed wiring boards and the like of electronic components.

従来例の構成とその問題点 近年、電子部品のチップ化が進み、とりわけコンデンサ
、抵抗等はその代表的なものであり、チップ形電子部品
の接続用端子としての外部電極はプリント基板装着時に
おける半田付は性、半田耐熱性の向上が重要となってき
ている。
Conventional configurations and their problems In recent years, electronic components have become more and more chip-based, with capacitors, resistors, etc. being representative examples. Improving soldering properties and soldering heat resistance are becoming important.

第1図はその具体構成を示すようにセラミックを基板と
したチップ部品1にPct・含有率20〜30係のAq
−Pd合金を有する外部電極2を形成しもものである。
FIG. 1 shows the specific structure of a chip component 1 made of ceramic as a substrate, and Aq with a Pct content of 20 to 30.
The external electrode 2 may also be formed using a -Pd alloy.

以上のように構成されたチップ形電子部品の外部電極は
、銀くわれを防止するためにpb金含有多いのは周知の
ことであシ、そのためコストが高く、さらには昨今プリ
ント配線基板の半田付は条件が厳しくなり、半田槽への
浸漬回数の増加が一般的となっているだめAq−Pd外
部電極では半田耐熱性が充分保証できない欠点を有して
いた。
It is well known that the external electrodes of the chip-type electronic components configured as described above contain a large amount of PB gold to prevent silver corrosion, which increases the cost. The Aq-Pd external electrode has the disadvantage that soldering heat resistance cannot be sufficiently guaranteed because the conditions for attaching it are becoming stricter and the number of immersions in a soldering bath is generally increased.

一方、半、田耐熱性向上の観点から、A(JまたはAq
−Pd上にNiとSnまたはS n −P b電極層を
電解メッキにより形成する方法が提案されているが、N
i及びSnメッキ液がPH4及びPH1〜2の強酸を用
いるため耐酸性の高いガラスフリット(以下G、Fと云
う)全入qまだはAg−Pdに使用しなければならない
。現在、考えらiする耐酸性のG、F、はΔ1203.
SiO2等を多量に含む叱較的比重の軽いG、F、が用
いられる。そのだめ、電(壷焼付時に電極表面にG、F
、が浮き一ヒがり、Niメッキ時にメッキの付き回りが
悪く、Sn4だはpbのメッキ後の完成品で半田付は不
良が発生すると云う欠点を有していた。
On the other hand, from the viewpoint of improving the heat resistance of semi-finishing and soldering,
A method has been proposed in which a Ni and Sn or Sn-Pb electrode layer is formed on Pd by electrolytic plating, but N
Since the Sn and Sn plating solutions use strong acids with pH 4 and PH 1 to 2, highly acid-resistant glass frits (hereinafter referred to as G and F) must be used for Ag-Pd. Currently, the acid-resistant G and F considered are Δ1203.
G and F, which contain a large amount of SiO2 and the like and have relatively light specific gravity, are used. However, the electric current (G and F on the electrode surface when baking the pot)
, which had the disadvantages of floating and cracking, poor plating coverage during Ni plating, and failure of soldering in the finished product after Sn4 plating with PB.

発明の目的 本発明は、上記欠点に鑑みカラス含有率の異なる2種類
のAq電極層を形成し、その上に無電解まだは電角イメ
ツキによりN 1層を、さらにその上に電解メッキによ
りSnまたはS n −P b電極層を形成し、Pdi
使用せずに半田耐熱及び半田付は性の優れた外部電極を
形成する方法を提供するものである。
Purpose of the Invention In view of the above-mentioned drawbacks, the present invention has been developed by forming two types of Aq electrode layers with different glass contents, on which a N1 layer is formed by electroless or electroplating, and furthermore, a Sn layer is formed by electrolytic plating on top of the N1 layer. Or form a Sn-Pb electrode layer and
This provides a method for forming external electrodes with excellent heat resistance and soldering properties without using solder.

発明の構成 この目的を達成するために本発明のチップ部品の外部電
極形成方法は、半田耐熱の優れたメッキ処理を前提とし
、耐酸性の優れたG、F、を7〜20%含有する第1A
q電極層を形成し、その」二に比重が比較的大きくガラ
スの浮き上りが少ないG、F、力ゝ゛2〜4%の第2 
A g電極層が構成されておシ、さらにその上の第3電
極層及び第4電極層はそれぞれNi及びSniだばS 
n −P bから構成されている。この構成によれば、
半田付は性、半田耐熱性に優れた外部電極を有するチッ
プ部品を得ることができる。
Structure of the Invention In order to achieve this object, the method for forming external electrodes of chip components of the present invention is based on the premise of a plating process with excellent solder heat resistance, and a method for forming external electrodes of chip components using a method of forming external electrodes of a chip component containing 7 to 20% of G and F, which have excellent acid resistance. 1A
The q electrode layer is formed, and the second layer is G, F, which has a relatively large specific gravity and little glass lifting, and the second layer has a force of 2 to 4%.
The third electrode layer and the fourth electrode layer thereon are made of Ni and Sni, respectively.
It is composed of n-Pb. According to this configuration,
Chip components having external electrodes with excellent soldering properties and soldering heat resistance can be obtained.

実施例の説明 以下、本発明の一実施例について図面を参照しながら説
明する。第2図は本発明の一実施例におけるチップ部品
の外部電極の断面状態を示すものである。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows a cross-sectional state of an external electrode of a chip component in an embodiment of the present invention.

第2図において、1は第1図と同じくセラミックを基板
とするチップ部品、3はS i02+Al203)主成
分とするG 、 F 、 i7〜20%含有した第1A
g電極層である。4はP bo T S 102を主成
分とするG、F、全2〜4%含有した第2 A g電極
層である。5は電解メッギ捷たは無電解メッキにより形
成された第3電極層としてのNi層、6は電解メッキに
より形成された第4電極層としてのSnまだはS n 
−P b層である。第3図はメッキ液浸せき6層分後の
電極接着強度と第1電極層3におけるG、F、含有率と
の関係を示したものである。第4図においてはNfメッ
キの利き回りをX線マイクロアナライザーにて第2電極
層4におけるG、F、含有率とS i / A g比の
関係を表面元素分析したものである。Si/Ag比が6
係以下のとき第3電極層、第4電極層をメッキ形成する
ことにより、半田付は性は良好で、98%以上の半田付
は性を得る。
In FIG. 2, 1 is a chip component having a ceramic substrate as in FIG. 1, and 3 is a first A containing 7 to 20% of G, F, and i as main components (Si02+Al203).
g electrode layer. 4 is a second Ag electrode layer containing G and F whose main components are P bo T S 102 in a total amount of 2 to 4%. 5 is a Ni layer as a third electrode layer formed by electrolytic plating or electroless plating, and 6 is a Sn layer as a fourth electrode layer formed by electrolytic plating.
-P b layer. FIG. 3 shows the relationship between the electrode adhesion strength after six layers of plating and the G, F, and content rates in the first electrode layer 3. In FIG. 4, the Nf plating yield is obtained by surface elemental analysis of the relationship between the G, F, content and S i /A g ratio in the second electrode layer 4 using an X-ray microanalyzer. Si/Ag ratio is 6
By forming the third electrode layer and the fourth electrode layer by plating when the temperature is less than 98%, the solderability is good, and the solderability is 98% or more.

第1Aq電極層3のG、F、含有率が7係未満では、第
3図のデータでわかるように電極接着強度が1Kg /
 cnf以下となり、完成品後の外部電極端子としての
強度が劣るため、品質が低下する。また、G、、F、含
有率が20.%を超えると、ガラス成分が表面析出し、
第2八q電極層4との密着性が低下する。そして、第2
八q電極層4のG、F含有率が4係を超えた時には、ガ
ラス成分が表面に浮き、メッキの付き回りが悪くなり、
またG。
When the content of G and F in the first Aq electrode layer 3 is less than 7 parts, the electrode adhesion strength is 1Kg /
cnf or less, and the strength of the finished product as an external electrode terminal is poor, resulting in a decrease in quality. In addition, the content of G, , F is 20. %, glass components will precipitate on the surface,
Adhesion with the second 8th q electrode layer 4 decreases. And the second
When the G and F content of the 8q electrode layer 4 exceeds 4 parts, the glass component floats to the surface and the coverage of the plating becomes poor.
G again.

F、含有率が2%未満では、ガラス成分による接着効果
が低下するため、第1Ag電極層3との密着性が悪くな
る。
If the content of F is less than 2%, the adhesive effect due to the glass component is reduced, resulting in poor adhesion to the first Ag electrode layer 3.

このように第1電極層に耐酸性の優れたG 、 F。In this way, G and F have excellent acid resistance in the first electrode layer.

7〜20%含有するAq電極層を形成し、第2電極層に
G、F、2〜4係含有するAg電極層全形成した上に第
3電極層、第4電極層をメッキ形成したものは、電極接
着強度1.OK9/ rtU以上を有し、かつ半田付は
性は98%以上を確保し得る。以上のように第1電極層
をG、F、7〜20%を含有する銀で形成し、第2電極
層をG、F、2〜4%含有する銀で形成し、さらに第3
電極層、第4電極層をメッキにより形成する方法による
と、セラミック基板との接着強度に優れ、かつ半田耐熱
性及び半田付は性の優れた外部電極を得ることが可能と
なった。
An Aq electrode layer containing 7 to 20% is formed, a second electrode layer is entirely formed with an Ag electrode layer containing G, F, and 2 to 4%, and then a third electrode layer and a fourth electrode layer are plated. is the electrode adhesion strength 1. It has OK9/rtU or more and can ensure solderability of 98% or more. As described above, the first electrode layer is formed of silver containing 7 to 20% of G and F, the second electrode layer is formed of silver containing 2 to 4% of G and F, and the third electrode layer is formed of silver containing 2 to 4% of G and F.
According to the method of forming the electrode layer and the fourth electrode layer by plating, it has become possible to obtain an external electrode that has excellent adhesive strength with the ceramic substrate, and has excellent solder heat resistance and solderability.

発明の効果 以上のように本発明によれば、安価で、半田付は性、半
田耐熱性に優れた外部電極を有するチッ70部品の提供
が可能であり、その産業的価値は極めて犬である。
Effects of the Invention As described above, according to the present invention, it is possible to provide a chip 70 component having an external electrode that is inexpensive, has excellent solderability and soldering heat resistance, and its industrial value is extremely high. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のチップ6部品の断面図、第2図は本発明
方法の実施例におけるチック0部品の断面図、第3図は
本発明を説明するためのメッキ液60分間浸せき後の接
着強度をG、F、含有率との関係で示す図、第4図は同
じ<XMAによるG、F。 含有率とS i / A g比の関係を示す表面元素分
析図である。 1・・・・・・セラミックを基板とするチップ部品、3
・・・・・・第1Ag電極層、4・・・・・・第2AC
!電極層、5・・・・・・Ni層、6・・・・・・Sn
4たは5n−Pb層。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 ! =27− 第3図 −・りパラスフ1ノットイ1有李(φう第4図 −グラスフリ・ソト分有卑(6/−ン
Fig. 1 is a sectional view of a conventional 6-chip component, Fig. 2 is a sectional view of a 0-tick part in an embodiment of the method of the present invention, and Fig. 3 is an adhesion after being immersed in a plating solution for 60 minutes to explain the present invention. Figure 4 shows the relationship between strength and content of G, F, and content. FIG. 3 is a surface elemental analysis diagram showing the relationship between content and S i /A g ratio. 1...Chip parts using ceramic as a substrate, 3
. . . 1st Ag electrode layer, 4 . . . 2nd AC
! Electrode layer, 5...Ni layer, 6...Sn
4 or 5n-Pb layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure! =27- Fig. 3 - Riparasufu 1 not toi 1 ari (φ)

Claims (1)

【特許請求の範囲】[Claims] セラミックを基板とするチップ部品の外部接続用電極を
形成するに当シ、第1電極層として銀80〜93%、ガ
ラス成分20〜7%からなる電極層を形成し、第2電極
層に銀96〜98%、ガラス成分4〜2チからなる電極
層を、その上に電解メッキまたは無電解メッキにより第
3電極層としてNi層を、さらにその上に第4電極層と
して電解メッキによシSnまたはS n −P bから
なる電極層を形成することを特徴とするチップ形電子部
品の外部電極形成方法。
When forming external connection electrodes for chip components using ceramic as a substrate, an electrode layer consisting of 80 to 93% silver and 20 to 7% glass is formed as the first electrode layer, and silver is used as the second electrode layer. An electrode layer consisting of 96 to 98% glass and 4 to 2 pieces of glass is formed by electrolytic plating or electroless plating to form a third electrode layer of Ni, and on top of that a Ni layer is formed by electrolytic plating as a fourth electrode layer. A method for forming an external electrode of a chip-shaped electronic component, comprising forming an electrode layer made of Sn or Sn-Pb.
JP18174882A 1982-10-15 1982-10-15 Method of forming external electrode of chip type electronicpart Pending JPS5969908A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18174882A JPS5969908A (en) 1982-10-15 1982-10-15 Method of forming external electrode of chip type electronicpart

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18174882A JPS5969908A (en) 1982-10-15 1982-10-15 Method of forming external electrode of chip type electronicpart

Publications (1)

Publication Number Publication Date
JPS5969908A true JPS5969908A (en) 1984-04-20

Family

ID=16106188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18174882A Pending JPS5969908A (en) 1982-10-15 1982-10-15 Method of forming external electrode of chip type electronicpart

Country Status (1)

Country Link
JP (1) JPS5969908A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02281711A (en) * 1989-04-24 1990-11-19 Alps Electric Co Ltd Electrode formation of chip parts

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02281711A (en) * 1989-04-24 1990-11-19 Alps Electric Co Ltd Electrode formation of chip parts

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