JPS59191612A - Input and output designating system of sequence controller - Google Patents

Input and output designating system of sequence controller

Info

Publication number
JPS59191612A
JPS59191612A JP58065662A JP6566283A JPS59191612A JP S59191612 A JPS59191612 A JP S59191612A JP 58065662 A JP58065662 A JP 58065662A JP 6566283 A JP6566283 A JP 6566283A JP S59191612 A JPS59191612 A JP S59191612A
Authority
JP
Japan
Prior art keywords
input
output
counter
address space
designation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58065662A
Other languages
Japanese (ja)
Inventor
Shinichi Hachiya
蜂屋　真一
Katsuhiro Fujiwara
克弘 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58065662A priority Critical patent/JPS59191612A/en
Publication of JPS59191612A publication Critical patent/JPS59191612A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/054—Input/output
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To switch the designation for an input/output address space by providing an instruction processing progress state memory part to show the progress state of an instruction processing and switching the designation for the input/ output address space with a combination of the output of said memory part and an operation code. CONSTITUTION:A 2-bit counter 5 and a counter decoder 6 which decodes the output of the counter 5 are provided within an arithmetic control part 2. The decoded value (f) of the decoder 6 is supplied to an input/output space designating part 3. In addition, an operation code decoder 7 is provided within the part 2 to decode the operation code (a). The decoded value (e) of the decoder 7 is delivered to the part 3. Here an instruction processing progress state memory part is formed by the counter 5 and the decoder 6. The counter 5 counts up with a basic clock showing the minimum unit of the arithmetic processing. Then the processing is through with an instruction when the counter 5 counts up four times. The operation proceeds to the next instruction processing. Thus the designation is switched for the input/output address space in accordance with the state of the counter 5.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、ストアードプログラム方式のシーケンスコン
トローラの入出力指定方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an input/output designation method for a stored program type sequence controller.

〔発明の背景〕[Background of the invention]

２ｃ〔 第１図は従来のシーケンスコントローラの入出力指定方
式の第１の例を示すブロック図である。2c [FIG. 1 is a block diagram showing a first example of an input/output designation method for a conventional sequence controller.

第１図において、ユーザメモリ１は予めユーザによって
プログラムされたデータを格納するもので、そのデータ
の内容は第２図に示す様に、制御内容を指定するオペコ
ードａと、その制御対象となる入出力アドレス空間４を
指定するオペランドｂに分けられる。オペコードａは、
図示する様に演算制御部２に入力され、オペランドｂは
入出力アドレス空間指定部３と入出力アドレス空間４に
入力される。In FIG. 1, a user memory 1 stores data programmed in advance by the user, and the contents of the data, as shown in FIG. It is divided into operand b that specifies output address space 4. Opcode a is
As shown in the figure, the operand b is input to the arithmetic control section 2, and the operand b is input to the input/output address space specifying section 3 and the input/output address space 4.

第１図に示す従来例では、入出力アドレス空間４の指定
切換は次の様に行なわれる。即ち、あらかじめユーザメ
モリ１にプログラムされた入出力アドレス空間指定切換
命令が読み出されると、演算制御部２が入出力アドレス
空間指定切換信号Ｃを出力する。入出力アドレス空間指
定部３は、上記入出力アドレス空間指定切換信号Ｃを受
けて、その時ユーザメモリｌから出力されているオペラ
ンドｂを取ｐ込み、オペランドｂの内容に基づい３ｔ１ で一本の出力線に“１″を出力し、一つの入出力アドレ
ス空間４を有効にする。これによって、複数の入出力ア
ドレス空間４のうち１個が指定され、入出力アドレス空
間の指定が切換えられる。In the conventional example shown in FIG. 1, the designation of the input/output address space 4 is switched as follows. That is, when the input/output address space designation switching command programmed in the user memory 1 in advance is read out, the arithmetic control section 2 outputs the input/output address space designation switching signal C. The input/output address space specifying unit 3 receives the input/output address space specifying switching signal C, takes in the operand b output from the user memory l at that time, and outputs one signal at 3t1 based on the contents of the operand b. Output "1" on the line to enable one input/output address space 4. As a result, one of the plurality of input/output address spaces 4 is designated, and the designation of the input/output address spaces is switched.

しかし、第１図に示す従来方式では、１命令の実行中に
入出力アドレス空間４の指定切換を行なうことはできず
、切換を行なう場合はあらかじめ入出力アドレス空間指
定切換命令をユーザメモリ１にプログラムしておく必要
がある。そのため、プログラム効率が低下し、処理速度
が低下するという欠点があった。However, in the conventional method shown in FIG. 1, it is not possible to switch the designation of the input/output address space 4 during the execution of one instruction, and when switching is required, an input/output address space designation switching command is written in the user memory 1 in advance. It needs to be programmed. As a result, there have been disadvantages in that program efficiency is lowered and processing speed is lowered.

第３図は、入出力アドレス空間指定切換命令を用いずに
、入出力アドレス空間４の指定切換を行う様にした従来
方式の第２の例を示す図である。FIG. 3 is a diagram showing a second example of the conventional system in which the designation of the input/output address space 4 is switched without using an input/output address space designation switching command.

第３図において、第１図と同一部分は同一符号を付して
その説明を省略する。第３図に示す第２の従来方式では
、入出力アドレス空間指定切換命令を用いる代わシに、
第４図に示す様にユーザプログラムｌのワード長を長く
シ、オペランド部分をｂ′分だけ増やし、このオペ２ン
ドｂ′を入出力アドレス空間指定部３に入力し、入出力
アドレス空間を切換える様にしている。In FIG. 3, the same parts as those in FIG. 1 are given the same reference numerals, and the explanation thereof will be omitted. In the second conventional method shown in FIG. 3, instead of using an input/output address space designation switching instruction,
As shown in Figure 4, the word length of the user program l is lengthened, the operand part is increased by b', and this second operand b' is input to the input/output address space specifying section 3 to switch the input/output address space. I'm doing it like that.

しかし、第２の従来方式では、第４図に斜線で示すオペ
ランドｂ′に相当する分だけ、余分なメモリ容量が必要
になシ、ユーザメモリ１に容量の大きいものが必要とな
シ、ユーザメモリ１のコストアップの原因となり、実装
スペースも大きくなる欠点があった。又、全てのプログ
ラムステップにおいて、オペランドｂ′が必要になるた
め、ユーザメモリ１の利用率が低下する欠点もあった。However, the second conventional method does not require an extra memory capacity corresponding to the operand b' indicated by diagonal lines in FIG. This has the drawback of increasing the cost of the memory 1 and increasing the mounting space. Furthermore, since the operand b' is required in every program step, there is also the drawback that the utilization rate of the user memory 1 is reduced.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、入出力アドレス空間指定切替命令等の
特定命令を用いず、かつユーザメモリのワード長を増加
する５となく、入出力アドレス空間の切換を可能にする
新しいシーケンスコントローラの入出力指定方式を提供
することにある。An object of the present invention is to provide a new sequence controller that enables switching of input/output address spaces without using specific commands such as input/output address space designation switching commands and without increasing the word length of user memory. The purpose is to provide a designation method.

〔発明の概要〕[Summary of the invention]

本発明のシーケンスコントローラの入出力指定方式は、
シーケンス制御プログラムをユーザメモリから順次読み
出し、そのオペコードとオペラン６１ ドに従って各種の演算処理を行なうことによって、−４
ｏシーケンス制御を実行するシーケンスコントローラに
おいて、一つの命令処理の進行状態を聚わす命令処理進
行状態記憶部を備え、かつ該命令処理進行状態記憶部の
出力とオペコードの組合せによって、入出力アドレス空
間の指定切換えを行なうことを特徴としている。The input/output designation method of the sequence controller of the present invention is as follows:
By sequentially reading the sequence control program from the user memory and performing various arithmetic operations according to the operation code and operand 61, -4
o A sequence controller that executes sequence control is equipped with an instruction processing progress state storage section that keeps track of the progress state of one instruction processing, and uses a combination of the output of the instruction processing progress state storage section and an operation code to control the input/output address space. The feature is that designated switching is performed.

〔発明の実施例〕[Embodiments of the invention]

以下添付の図面に示す実施例によｐ、更に詳細に本発明
について説明する。The present invention will be described in more detail below with reference to embodiments shown in the accompanying drawings.

第５図は本発明の一冥施例を示すブロック図でおυ、第
１図に示す従来例と同一部分は同一符号を付してその説
明を省略する。この実施例における特徴部分は、オペラ
ンドｂが入出力アドレス空間指定部３に入力されないか
わ９に、第６図に示す様に演算制御部２内［２ビツトの
カウンタ５とその出力をデコードするカウンタデコーダ
６を設け、カウンタデコーダ６のデコード値ｆを入出力
空間指定ｓ３に出力し、更に演算制御部２内にオペコー
ドａをデコードするオペコードデコーダ７６　任 を設け、そのデコード値ｅを同様に入出力空間指定部３
に出力することである。カウンタ５とカウンタデコーダ
６は前記した命令処理進行状態記憶部に相当するもので
あシ、カウンタ５は演算処理の最小単位を表わす基本ク
ロックによって、カウントアンプする。カウンタ５が４
回カウントアンプすると、■命令の処理が終了し、次の
命令処理に入るものである。FIG. 5 is a block diagram showing one embodiment of the present invention, and the same parts as those of the conventional example shown in FIG. 1 are given the same reference numerals and the explanation thereof will be omitted. The characteristic part of this embodiment is that, even though operand b is not input to the input/output address space specifying section 3, as shown in FIG. A decoder 6 is provided to output the decoded value f of the counter decoder 6 to the input/output space designation s3, and an operation code decoder 76 for decoding the operation code a is provided in the arithmetic control unit 2, and the decoded value e is similarly input/output. Space designation part 3
It is to output to. The counter 5 and counter decoder 6 correspond to the above-mentioned instruction processing progress state storage section, and the counter 5 performs count amplification using a basic clock representing the minimum unit of arithmetic processing. counter 5 is 4
When the number of times is counted and amplified, the processing of the (1) instruction is completed and the processing of the next instruction begins.

第６図に示す様に、カウンタデコーダ６のデコード値ｆ
のうち現在有効１ｃなっている一つヲｃｏトし、オペコ
ードデコーダ７のデコード値ｅのうち現在有効になって
いる一つをＸとし、ｃｏとＸのアンド条件を取った信号
ｄｏＩ／ｃよって、入出力アドレス空間４のうちの一つ
が指定される。As shown in FIG. 6, the decoded value f of the counter decoder 6
Of these, one of them is currently valid 1c, and one of the decoded values e of the operation code decoder 7, which is currently valid, is X, and the signal doI/c is obtained by taking the AND condition of co and X. , one of the input/output address spaces 4 is designated.

以上の説明から明らかな様に、本実施例によれば、ある
オペコードａに対して、その演算処理過程を示すカウン
タ５の状態によって、入出力アドレス空間の指定切換え
ができ、従来方式の様な特定命令やワード長増加が不要
になる。As is clear from the above explanation, according to this embodiment, the designation of the input/output address space can be switched depending on the state of the counter 5 indicating the arithmetic processing process for a certain operation code a, which is different from the conventional method. Specific instructions and word length increases are no longer required.

〔発明の効果〕〔Effect of the invention〕

７Ｏｒ 本発明によれば、特定命令を用いず、かつユーザプログ
ラムメモリのワード長を増加することなく、入出力アド
レス空間の指定切換えが行なえる。According to the present invention, input/output address space designation can be switched without using a specific instruction and without increasing the word length of the user program memory.

従って、１処理の中で入出力アドレス空間指定切換えを
２回行なう様なプログラムを組む場合、第１図に示す従
来方式では、［命令１．切換命令。Therefore, when creating a program that switches input/output address space designation twice in one process, the conventional method shown in FIG. Switching command.

命令２．切換命令、命令３」の５命令のプログラムが必
要であったが、本発明によれば、ｌ命令のプログラムで
可能となる。従って、この例では、５倍のプログラム効
率の向上を図ることができる。Command 2. A program of 5 instructions (switching instruction, instruction 3) was required, but according to the present invention, this can be done with a program of 1 instruction. Therefore, in this example, the program efficiency can be improved five times.

また、第３図に示す従来方式で上記プログラムを組む場
合、［命令１．命令２．命令３」の３命令のプログラム
が必要であったが、本発明では上記した様に１命令です
むため、３倍のプログラム効率の向上になる。Furthermore, when building the above program using the conventional method shown in FIG. 3, [Instruction 1. Command 2. A three-instruction program (instruction 3) was required, but in the present invention, only one instruction is required as described above, resulting in a three-fold improvement in program efficiency.

更に、通常シーケンスコントローラは、４キロワ一ド程
度のユーザメモリを持っているため、例えばワード長を
２ピット長くすると、第４図に斜線でポス様に８キロピ
ツトのメモリ容量が余分に必要となる。しかし、本発明
によれば、これも不要となり、コストアップと笑装スペ
ースの増大を防止することができる。Furthermore, since a sequence controller normally has a user memory of about 4 kilobytes, for example, if the word length is increased by 2 pits, an additional 8 kilopits of memory capacity will be required as indicated by diagonal lines in Figure 4. . However, according to the present invention, this is no longer necessary, and an increase in cost and storage space can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のシーケンスコントローラの入出力指定方
式の第１の例を示すブロック図、第２図は第１図に示す
ユーザメ七りの構成図、第３図は従来のシーケンスコン
トローラの入出力指定方式の第２の例を示すブロック図
、第４図は第３図に示すユーザメモリの構成図、第５図
は本発明のシーケンスコントローラの入出力指定方式の
一実施例を示すブロック図、第６図は第５図に示す演算
制御部と入出力アドレス空間指定部の具体的構成を示す
図である。 ｌ・・・ユーザメモリ、２・・・演算制御部、３・・・
入出力アドレス空間指定部、４・・・入出力アドレス空
間、５・・・カウンタ、６・・・カウンタデコーダ、７
・・・オペコードデコーダ。 代理人　弁理士　秋　本　正　実 第１図 第２図 第３図 第４図Figure 1 is a block diagram showing the first example of the input/output specification method of a conventional sequence controller, Figure 2 is a configuration diagram of the user interface shown in Figure 1, and Figure 3 is the input/output of a conventional sequence controller. A block diagram showing a second example of the specification method, FIG. 4 is a configuration diagram of the user memory shown in FIG. 3, and FIG. 5 is a block diagram showing an embodiment of the input/output specification method of the sequence controller of the present invention. FIG. 6 is a diagram showing a specific configuration of the arithmetic control section and input/output address space designation section shown in FIG. 5. l...User memory, 2...Calculation control unit, 3...
Input/output address space specification section, 4... Input/output address space, 5... Counter, 6... Counter decoder, 7
...Opcode decoder. Agent Patent Attorney Tadashi Akimoto Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] シーケンス制御プログラムをユーザメモリから順次読み
出して、そのオペコードとオペランドに従って各種の演
算処理を行なうことによって、一連のシーケンス制御を
実行するシーケンスコントローラにおいて、一つの命令
処理の進行状態を表わす命令処理進行状態記憶部を備え
、かつ該命令処理進行状態記憶部とオペコードの組合せ
により、入出力アドレス空間指定切換えを行なうことを
特徴とするシーケンスコン）ＣＩ−ラの入出力指定方式
。In a sequence controller that executes a series of sequence controls by sequentially reading a sequence control program from user memory and performing various arithmetic operations according to its opcodes and operands, an instruction processing progress state memory that represents the progress state of one instruction processing. 1. An input/output designation system for a sequence controller (1), characterized in that the input/output address space designation is switched by a combination of the instruction processing progress state storage part and an operation code.
JP58065662A 1983-04-15 1983-04-15 Input and output designating system of sequence controller Pending JPS59191612A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58065662A JPS59191612A (en) 1983-04-15 1983-04-15 Input and output designating system of sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58065662A JPS59191612A (en) 1983-04-15 1983-04-15 Input and output designating system of sequence controller

Publications (1)

Publication Number Publication Date
JPS59191612A true JPS59191612A (en) 1984-10-30

Family

ID=13293423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58065662A Pending JPS59191612A (en) 1983-04-15 1983-04-15 Input and output designating system of sequence controller

Country Status (1)

Country Link
JP (1) JPS59191612A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989011686A1 (en) * 1988-05-19 1989-11-30 Fanuc Ltd System for making reference to signals of a pc unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989011686A1 (en) * 1988-05-19 1989-11-30 Fanuc Ltd System for making reference to signals of a pc unit

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