JPS62125435A - Microprogram control system - Google Patents

Abstract

PURPOSE:To produce a long literal without increasing the word length of a microinstruction by using a control microinstruction stored in a certain field in a microinstruction to detect and hold the information on production of the long literal if contained in the microinstruction to be executed next and defining a certain specific field as a constant field during execution of the next microinstruction. CONSTITUTION:If it is shown that the next microinstruction orders the transfer of a long literal, a CNT field 104 holds the data showing the information on production of the long literal. Then the coincidence between the bit patterns of said data is decoded and detected by a CNT field decoder 108 and the information on production of the long literal is produced. The output of a holding circuit 109 is set at logic '1' based on said information and the long literal production signal LLIT is produced. This signal LLIT is held during an executing period of the next microinstruction. Thus a long literal is produced in the executing period of the next microinstruction and delivered to an internal bus 111.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control system, and more particularly to a microprogram control system for constant fields within microinstructions.

[Conventional technology]

Generally, in a microprogram control device, a microprogram consisting of a series of microinstructions is stored in a control storage unit, and is sequentially read out each time a microinstruction is executed and temporarily held in a microinstruction register. The output of is decoded and a micro-order containing the information specified by the micro-operation instruction is generated and provided to each control point.

In addition, the format of microinstructions is divided into arithmetic fields related to arithmetic operations, branch control fields related to branching, constant fields for branch address arithmetic, and control fields for control points that cannot be controlled by arithmetic instructions or branch instructions. It consists of one command word. Furthermore, the operation field is generally divided into fields such as transfer, addition/subtraction, multiplication/division, logical operation, and shift.

In addition, in order to increase the word length of the microinstruction and to minimize the capacity of the control storage unit, the number of constant fields is
Basic term for data processing Long, for example, the internal bus bit width is 1
(6 bits to 32 bits) (for example, about 8 bits compared to the basic word length of 16 to 32 bits).

(For example, Microprogramming, Hiroshi Hagiwara, 1977
(2010, pp. 35-68, pp. 287-333) Next, an example of a conventional microinstruction format, particularly the structure of a constant field, will be explained with reference to the drawings.

FIG. 2 is a format diagram showing an example of a conventional microinstruction format, and FIG. 3 is a format diagram showing an example of an operation field format.

The conventional microinstruction format, as shown in FIG. 2, is composed of an OP field 201 indicating an operation field, a CNT field 202 indicating branch or control, and an LIT field 203 indicating a constant field.

Furthermore, as shown in FIG. 3, the OP field 201 is a field indicating the type of instruction.
1. The DST field 302 is a field that indicates the code of the side where data is transferred (register address, etc.), and the field that indicates the code of the side that sends data (register address or control information for sending constants, etc.). It is divided into a certain SRC field 303,
Conventionally, the operation indicated by the data stored in the OPC field 301 is a transfer command, and the SRC field 303
If control information for sending a constant is stored in the register specified by the DST field 302, the L
Constants stored in the IT field were being transferred.

[Problem that the invention seeks to solve]

In the conventional microprogram control method described above, the configuration of the constant field at the time of constant transfer is a fixed data length, and the constant field and the constant field 1 are used to increase the data length. When generating a long literal that indicates a value larger than a literal that indicates a value that can be expressed in a constant field because there is no control field data that indicates that the The disadvantage is that it has to be generated.

FIG. 5 is a flowchart showing an example of a conventional long literal generation microprogram.

Here, for example, 24 bit wide registers R1 and R2
The following explanation assumes that the data length is 8 bits, and each step is A to G.

Step A: Transfer the 8-bit literal to register R1.

Stator B: Shifts the literal in register R1 to the left by 8 bits.

Step C: Transfer another 8-bit literal to register R2.

Step D=OR the literals of register R1 and register R2 and hold it in register R1.

Step E Shift the literal in register R1 obtained in step D to the left by 8.

Steg F: R2 another 8-bit literal
Transfer to.

Step G: Take the logical sum of register R1 and register R2 and hold it in register R1.

As mentioned above, it takes seven steps to generate a long literal. In order to reduce this number of sterafs,
For example, the following improvement methods can be considered.

FIG. 4 is a format diagram showing an example of the improved microinstruction format. This is the conventional microinstruction format shown in FIG. 2, with an ID bit 401 indicating switching between a mode in which literals are not used and a mode in which literals are used.

Now, when ID pill-401 is 0, each independent field is normally decoded to generate a micro-order,
When ID BiSoto 401 is 1, CNT field 40
3 and the LIT field 404 can generate a long literal that is larger than the literal in the literal field T field 404.

However, even with the above construction method, r
There is a drawback that the capacity of the control storage section increases by the amount corresponding to Dpi.

An object of the present invention is to detect and retain information when a microinstruction to be executed next by a control microinstruction stored in a certain field in a microinstruction contains information that generates a long literal. By making a certain field a constant field during the execution of the microinstruction,
It is possible to generate long literals without increasing the word length of microinstructions, and with only a small increase in hardware, long literals with longer data lengths can be generated, and the number of microinstruction steps can be reduced to i'! The object of the present invention is to provide a microprogram method that can reduce the amount by one.

Means for Solving Problem L] The microprogram control system of the present invention includes a control storage section that stores microinstructions constituting a microprogram, and a microprogram control system that stores microinstructions constituting a microprogram, and a microprogram control system that stores microinstructions constituting a microprogram. In a microprogram control system for a control device that includes a microinstruction register that temporarily holds instructions, and a control device that decodes each field data divided into a plurality of fields of the microinstruction and generates a microorder that gives instructions to each control point, a decoder that detects a match between the bit pattern of the field data and a predetermined bit pattern; and a decoder that retains the information detected by the decoder during the next microinstruction execution period and uses the information to control the controller. A holding circuit is provided for disabling the decoding function of a particular field and generating a control signal for using the disabled field as a constant field.

Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The control storage unit 100 holds a plurality of microinstructions constituting a microprogram. The microinstructions read from the control storage section 100 are temporarily held in the microinstruction register 114. The microinstruction includes an OPC field 101 .
DS' field 102 and SRC field 1
．． It consists of an oP field consisting of 03, a CNT field 104 indicating branching or control, and a LIT field 105 indicating a constant field.

Decoders for decoding each of the above field data include an OPC field decoder 115, a DST field decoder 106, an SRC field decoder 107, and a CNT field decoder 108.

The holding circuit 109 detects information indicating that the instruction to be executed when the next microinstruction is executed uses a long literal, and generates the detection information signal, that is, the long literal generation signal LLIT.

The constant synthesizer 11 - 0 generates a literal or a long literal using a signal SLIT indicating literal generation without using a long literal or a long literal generation signal LLIT using a long literal, and outputs it to the internal bus 111 .

Literals or long literals output to the internal bus are
The data is transferred to the internal register 113 indicated by the data in the DST field 102 and held there. At this time, DST
The data in field 102 is decoded by DST field decoder 106 and write gate 112 to internal register 113 is opened.

Next, a case where the operation is a transfer instruction will be considered and explained in detail.

A predetermined bit pattern is used as data indicating long literal generation, and the bit pattern of a certain field data is
・The pattern (that is, information indicating literal generation) is S
It shall be held in the RC field 103.

First, field data of the OPC field 101, DST field 102, SRC field 103, and CNT field 104 of the microinstruction read from the control storage unit 100 and temporarily held in the microregister 114 each time the microinstruction is executed is OPC field decoder 115, DST field decoder 10
6. Decoded by the SRC field decoder 107 and the CNT field decoder 108. At this time, holding circuit 109 does not operate.

If the next microinstruction is an instruction to transfer a long literal, data indicating long literal generation information is held in the CNT field 104, and the CNT field decoder 108 decodes the bit pattern matching of the data. Detected, information indicating long literal generation is generated, and the output of the holding circuit 109 becomes logic ゛°1'' due to the information, and the long literal generation signal LLI
T is generated and held during the first microinstruction execution period.

Then, when the next microinstruction execution period begins, the long literal generation signal LLIT is held at logic "1", so the decoding functions of the SRC field decoder 107 and the CNT field decoder 108 are disabled.
That is, decoding is prohibited and the SRC field 103
, CNT field 104 are invalidated, and constant synthesizer 110 interprets SRC field 103, CNT field 104, and LIT field 105 as constant fields, generates a long literal, and outputs it to internal bus 111.

The long literal output to the internal bus 111 is DST
The data is transferred to and held in the internal register 113 indicated by the data in field 102. At this time, the write gate 112 of this register 113 is connected to the DST field decoder 1.
It is opened by 06.

FIG. 6 is a flowchart showing a microprogram for generating a long literal according to the present invention.

Here, DST field 102, CNT field 1
04 and LIT field 105 are considered to be long literals whose widths are 8 bits and 24 bits, respectively. Also, assuming register R1, long literal transfer is executed.

Suffix 31 Indicates that the microinstruction to be executed next uses a long literal.

Step b: Transfer the 24 bit long literal to register R1.

As is clear from a comparison between FIG. 5 and FIG. 6, it conventionally required seven steps to generate a microprogram.

Since the present invention utilizes long literal generation, there are only two steps, and the number of microinstruction steps and execution time can be significantly reduced. Although the above embodiment has been explained using an example of a transfer instruction, it can also be applied to expanding the branch destination address width of a two-branch alloy of arithmetic instructions using constants.

〔Effect of the invention〕

As explained above, the present invention is a control microinstruction stored in a certain field in a microinstruction, and when the content of the microinstruction to be executed next includes information for generating a long literal, the information is By detecting this and making a certain field a constant field during the execution of the next microinstruction, it is possible to generate a long literal without increasing the word length of the microinstruction, resulting in a small increase in hardware. This has the effect of generating a long literal with a longer data length and drastically reducing the number of microinstruction steps.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a conventional microinstruction format diagram, Fig. 3 is an arithmetic field format diagram, and Fig. 4 is a microinstruction format different from Fig. 2. An example of a diagram, FIG. 5 is an example of a flowchart for generating a long literal using the α instruction in a conventional micro, and FIG. 6 is an example of a procedure for generating a long literal using a micro instruction according to the present invention. FIG. 1. OO...Control storage unit, 101...OPC field, 102...DST field, 103...
SRC field, 104...CN "T" field, 105...LIT field, 105...D
S T field decoder, 107...SRC field decoder, 108...CNT field decoder, 109...Member circuit, 110...Constant synthesizer, 1
DESCRIPTION OF SYMBOLS 11... Internal value 112... Write gate to register, 113... Internal register, 114... Micro-instruction register, 115... OPC field decoder, 201... CP field, 202... C.N.T.
Field, 203... LIT field, 301.
・OPC field, 302...DST field,
303...SRC field, 401...ID bit, 402...OP field, 403...CNT
Field, 404...LIT field.

Claims (1)

[Claims] A control storage unit that stores microinstructions constituting a microprogram, a microinstruction register that temporarily holds microinstructions read from the control storage unit each time each microinstruction is executed, and the microinstructions divided into a plurality of fields. A decoder that detects a match between a bit pattern of a certain field data and a predetermined bit pattern in a microprogram control method of a control device that decodes each field data and generates a micro order that gives instructions to each control point. and retaining the information detected by the decoder during the next microinstruction execution period, disabling the decoding function of a certain field of the control device using the information, and using the disabled field as a constant field. A microprogram control method characterized by comprising a holding circuit that generates a control signal for the control.