JPS59188768A - Storage device - Google Patents

Abstract

PURPOSE:To make maintenance and adjustment easy by providing a control card mounting altogether the hardware for controlling each memory card to make the memory card comparatively simple. CONSTITUTION:The control card is provided in addition to the memory cards in a storage device provided with the plural memory cards mounting a prescribed number of memory units and specifying a desired unit through the address designation from a CPU. This memory card includes a unit packaging information storage device and a decoder for designating unit, the control card is provided with adders ADD1-ADD5 having nearly equal number to the memory card number and comparators CMPphi-CMP5, and the adders hold the total of the packaging capacity of the cards up to the preceding stage and the capacity of the own card, the grand total is used as one input to the comparators, an address designated by the CPU is used as the other input of the comparators for attaining comparison to access the desired memory unit.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention has a plurality of memory cards forming a memory unit, and a control card provided outside the memory cards is equipped with a card access circuit only on the control card. Regarding storage devices.

(2) Prior art and problems Conventionally, a storage device that operates while being connected to a central processing unit is
As shown in the figure, it is often implemented as a memory card. A predetermined number of memory units, such as one or four, are provided in the memory card MMC. Each memory card has a built-in register RG, adder AD, and comparator CMP in order to access the memory card MMC. Initially, all "0" signals are input from the central processing unit to clear all contents of the register. Then for the original card MMCI a +1 signal equal to the number of memory units MU, in this case "4".
” is set in the sending register RGI from the central processing unit. The second card MMC2 is the register R of the first card.
The contents of GI are read, and the value and a +1 signal equal to the number of memory units MU in the own card, in this case "2", are added in adder AD2, and the obtained "6" is placed in register RG2. Repeat this for the third card MMC3 and below. When a memory card is accessed from the central processing unit, a predetermined card can be quickly selected by comparing the address value and the value of the register RG in each memory card using each comparator CMP. However, in this method, the same hardware is used for each memory card regardless of the number of memory units, so the amount of hardware increases as the number of memory cards increases; and the number of units installed cannot be changed at a later stage. This will have an immediate impact on registers on cards.

(3) Purpose of the Invention The purpose of the present invention is to improve the above-mentioned drawbacks, simplify the structure of the memory card, provide the control card with hardware for controlling the operation of the memory card, and simplify the overall structure and operation. The objective is to provide a storage device with

(4) Structure of the Invention The structure of the present invention for achieving the above-mentioned object includes a plurality of memory cards each carrying a predetermined number of memory units,
In a storage device that specifies a desired unit by addressing from a central processing unit, a control card is provided outside the memory card, the memory card includes a unit mounting information storage device and a unit designation decoder, and the control card includes a memory It is equipped with a number of adders and comparators approximately equal to the number of cards, and the adder holds the sum of the installed capacitance values of the cards up to the previous stage and the total value of the capacitance values of its own card, and inputs one of the comparators. , the address specified by the central processing unit is compared with the other input of the comparator, and a predetermined memory unit can be accessed.

(5) Embodiment of the Invention An embodiment of the invention shown in the drawings will be described below. FIG. 2 shows an example of the structure of the memory card, and FIG. 3C shows an example of the structure of the control card. In FIG. 2, MUO to MU3 are memory units, each unit having the same capacity, and in this case, four units are mounted on the memory card. Of course, depending on the card, the number of units MU may be one or three.

For example, the capacity of one memory unit M0 is 256kW-n
Bit. SH8 is a memory unit mounting information storage device, AD is an adder, DEC is a unit specification decoder,
AND is a logical product operation circuit, TSB is a tri-state bus, and P-S is a converter that converts a parallel signal into a serial signal. As shown in the drawing of the configuration example of the control card in FIG.
LK is a clock control circuit provided in the central processing unit, and is connected to the memory unit mounting information storage device SH in FIG.
In order to control S, six clocks are generated immediately after the central processing unit is powered on. The clock is then applied to the parallel-to-serial converter p-s via the clock line CLKL in FIG. A card selection signal C8O is sent to the control card via the tri-state bus TSB with mounting information (in the example of FIG. 2, "000100" representing the decimal digit 4) as a serial signal. At this time, mounting information on other cards is also sequentially sent to the control card as card selection signals C81, C32, - as many serial bits as there are memory cards using the same clock. Figure 3 shows that there are six cards.

The control card shown in FIG.
DD5 and comparators CMPO to CMP5 are provided.

Five or six adders and comparators are provided, which is approximately equal to the number "6" of memory cards MMC. Converter (S-P) 0
In the memory card interval, the mounting information of 0 becomes a parallel signal and is sent to the adder. Here is the memory card number,
The implementation information of 1 is also input and added. One input in the comparator CMPO is the output of (S-P)0, and in the comparator CMP1, the output of (S-P)O, the output of (S-P)0, and the output of the adder AD
The output of DI is applied. In comparator CMP2, A
The output of DDI and ADD2 is applied. In this way, the output of the corresponding adder and the output of the previous adder are applied to the comparator CMP. The number of memory units is specified from the address information terminal ADR. For example, when it says "8", it can be determined which comparator's application output corresponds to the eighth memory unit in the card 110, so it can be determined that, for example, memory card No. 2 corresponds. This judgment is made from the comparator output to the tri-state bus TSB.
is transmitted in the opposite direction.1. Activate the specified memory card.

Since an address signal for selecting a unit in the memory card is applied to the terminal ADR in FIG. 2, it is decoded by the decoder DEC and operated by the AND operation circuit AND to select the memory unit. Actually, the lowest two bits of the address signal from the central processing unit are used.

The upper address focus is given to ADS in FIG. 2, and can specify a cell within the memory unit.

For example, when a memory unit has a capacity of 250 Ky, address bits 0 to 17 specify the address within the unit, and address bits 18 to 19 specify the memory unit. Tri-state buses help reduce the number of signal transmission lines. A timing control signal is actually required when accessing the memory, but it is not shown in the drawings because it is used in the same way as before. It can be determined completely arbitrarily whether to set the memory card number to NIL O or ffi 1.

(6) Effects of the Invention In this way, according to the present invention, since a control card is provided which is equipped with hardware for controlling each memory card, the memory card is relatively simple and requires maintenance and adjustment. It's easy to do.

For example, when adding or subtracting memory carts, it is sufficient to process only the control cards.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining conventional storage device access, FIG. 2 is a diagram showing the configuration of a memory card as an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of a control card as an embodiment of the present invention. It is a diagram. CPQ - Central processing unit MMC - Memory card MU - Memory unit RG - Register AI) - Adder CMP - Comparator 5H3 - Implementation information storage device D E C - Unit) tlt regular use Decoder AND・−
・Logic product operation circuit T S B-) License state bus cso,,csl-・-Card selection line Patent applicant Fujitsu Limited Agent Patent attorney Eisuke Suzuki 1st cause

Claims (1)

[Claims] In a storage device that has a plurality of memory cards equipped with a predetermined number of memory units, and specifies the desired unit by addressing from a central processing unit, a control card is provided outside the memory card, and the memory card has a unit mounted thereon. The control card includes an information storage device and a unit specification decoder, and is equipped with adders and comparators whose number is approximately equal to the number of memory cards. A storage device characterized in that a total capacitance value of is held and used as one input of a comparator, and an address specified by a central processing unit is used as the other input of the comparator for comparison, so that a predetermined memory unit can access it.