JPS59181725A - 抵抗結合形ジヨセフソンデコ−ダ - Google Patents

抵抗結合形ジヨセフソンデコ−ダ

Info

Publication number
JPS59181725A
JPS59181725A JP58053489A JP5348983A JPS59181725A JP S59181725 A JPS59181725 A JP S59181725A JP 58053489 A JP58053489 A JP 58053489A JP 5348983 A JP5348983 A JP 5348983A JP S59181725 A JPS59181725 A JP S59181725A
Authority
JP
Japan
Prior art keywords
circuit
input
gate
resistance
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58053489A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0155780B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Yoshifusa Wada
和田　容房
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP58053489A priority Critical patent/JPS59181725A/ja
Publication of JPS59181725A publication Critical patent/JPS59181725A/ja
Publication of JPH0155780B2 publication Critical patent/JPH0155780B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
    • H03K19/1954—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current
    • H03K19/1956—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current using an inductorless circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/001—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used
    • H03M7/003—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used using superconductive devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Logic Circuits (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
JP58053489A 1983-03-31 1983-03-31 抵抗結合形ジヨセフソンデコ−ダ Granted JPS59181725A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58053489A JPS59181725A (ja) 1983-03-31 1983-03-31 抵抗結合形ジヨセフソンデコ−ダ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58053489A JPS59181725A (ja) 1983-03-31 1983-03-31 抵抗結合形ジヨセフソンデコ−ダ

Publications (2)

Publication Number Publication Date
JPS59181725A true JPS59181725A (ja) 1984-10-16
JPH0155780B2 JPH0155780B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-11-27

Family

ID=12944250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58053489A Granted JPS59181725A (ja) 1983-03-31 1983-03-31 抵抗結合形ジヨセフソンデコ−ダ

Country Status (1)

Country Link
JP (1) JPS59181725A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61274422A (ja) * 1985-04-24 1986-12-04 Nec Corp ジョセフソン効果を用いた入出力分離回路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873094A (ja) * 1981-10-27 1983-05-02 Mitsubishi Electric Corp ジヨセフソン素子を用いたデコ−ダ回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873094A (ja) * 1981-10-27 1983-05-02 Mitsubishi Electric Corp ジヨセフソン素子を用いたデコ−ダ回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61274422A (ja) * 1985-04-24 1986-12-04 Nec Corp ジョセフソン効果を用いた入出力分離回路

Also Published As

Publication number Publication date
JPH0155780B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-11-27

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