JPS5917867B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a low noise junction field effect transistor (hereinafter referred to as J-FET) suitable for high integration.

) The present invention relates to a semiconductor integrated circuit device including at least the following. Traditionally, J-FETs have square-law characteristics and low noise characteristics.
Because it has characteristics that bipolar elements do not have, it is widely used in various fields including the acoustic field.

However, the J-FET in a semiconductor integrated circuit in which the J-FET is integrated with an element such as a bipolar transistor,
Unlike a single J-FET, it is extremely disadvantageous that it occupies a large area. One reason why a J-FET is incorporated into a semiconductor integrated circuit having a bipolar element is to enable lower noise than a bipolar transistor. On the other hand, this J-FET is required to carry the current required by other bipolar elements, and must also satisfy sufficient low noise performance. In order to satisfy this condition, a J-FET with small gate resistance and large transfer conductance (gm) is required, and a large area is required. is difficult to obtain. In other words, the J-FET, which requires the above-mentioned performance, requires about 15 to 20 times the area occupied in an integrated circuit compared to a bipolar transistor.
A plurality of J-FETs are formed in 20 to 5 parts of the entire integrated circuit.
Since it occupies 30% of the total area, the integrated circuit chip area increases, which is extremely disadvantageous to the production of integrated circuits. FIG. 1 shows an NchJ-FET with a back gate structure integrated with a bipolar element (not shown).

A J-FET incorporated in an integrated circuit employs a surface channel, Pwell back gate structure that allows formation of a channel region without performing heat treatment to the extent that the base width of the bipolar transistor changes. 1 is a p-type silicon substrate, 2 is an n-type epitaxial layer formed on the substrate 1, 3 is a P-Well formed in the n-type epitaxial layer 2 and serves as a gate, and 4 is a low resistance of P-Well 3 P channel stoppers 5 and 6 are n+ formed in P-Well 3 to eliminate contact and MOS effects.
type source/drain, 7 is an n channel connecting source 5 and drain 6, 8 is a p channel connected to P-Well 3
The + region becomes a surface gate.

9, 10, 11 are source, drain, gate electrodes, 12
13 is an insulating oxide film, and 13 is a p layer separating the epitaxial layer 2.
It is a shape separation area.

In the J-FET shown in FIG. 1, there is only one channel on one side of the opposing surfaces of the source 5 and drain 6, so in order to obtain a predetermined Gm, it is necessary to increase the channel width. be.

Therefore, as the area of the J-FET increases,
As the gate length of the east gate region becomes longer, the gate resistance increases. When the gate resistance increases in this way, there is a problem in that thermal noise increases. Therefore, J-
There is a method of forming a channel on both sides of the source 5 and drain 6 like a FET, and obtaining the necessary transfer conductance while substantially increasing the channel width and shortening the channel width y without significantly increasing the area. It is considered.

However, the FET in FIG. 2 has sources 5a and 5b.
, 5c1 drains 6a, 6b can be arranged to shorten the channel width y, thereby obtaining the necessary Gm and improving thermal noise characteristics. And if the performance is the same, the first
The area is about 70% compared to the figure. However, in this structure, the source 5 and drain 6 must be arranged alternately in the P-Well 3, and the number of contact parts for extracting the electrodes of the source 5 and drain 6 increases, and there is a limit to reducing the occupied area. be. In other words, normally 20 to 30 sources and drains are formed in one FET, and forming contacts to all of them requires a large area, and the contacts cover about 50% of the island-like area where the J-FET is formed. , wiring is provided. Therefore, J- in Figure 2
For FETs, the limit was to keep the occupied area to about 70% of that in Figure 1. The present invention reduces the number of contacts for taking out electrodes by electrically connecting a plurality of source or drain regions in a region outside an island-like region that becomes a gate region, and achieves the required Gm with a small occupied area. The present invention is also characterized by obtaining a J-FET having low noise characteristics.

FIG. 3 shows a J-FET fabricated in a semiconductor integrated circuit according to an embodiment of the present invention.

In FIG. 3, 101 is a p-type silicon substrate, and 102 is a resistor formed on the p-type substrate 101 with a resistivity of 1 to 3 Ω-? n of
An n-type island region consisting of a type epitaxial layer in which J-
FET is built in. Reference numeral 103 indicates a p-type island-like region (hereinafter referred to as P-Well) formed in the n-type island region 102, which serves as a back gate and has a layer resistance of 2 to 4K (zero) and a diffusion depth of 3 to 4 μm.

), 105 (105a, 105b) are n-type source regions formed in 103, and 106 (106a, 10
6b, 106c) are the island region 102 and the gate region 103a
, 103b, an electrode contact is formed only in region 106a,
They are electrically connected to each other by the island regions 102 as shown by dotted lines. 107 (107a, 107b, 107c, 1
07d) is the gate region 103 between the source and drain regions.
Layer resistance formed within 3-5 capsules/mouth, diffusion depth 0.5μ
An n-type channel region 108 of m to 1.0 μm is formed in the channel region and connected to the gate region 103,
Layer resistance 1 to several 100Ω/hole, depth 0.05μ to 0
．． This is a 3μ p-type heavily doped surface gate region.

Formation of this surface gate substantially determines the transfer conductance Gm of the J-FET. 109,
110 is an electrode wiring for the source region 105 and drain region 106; 112 is an insulating oxide film formed on the p-type substrate 101; and 113 is for separating the epitaxial layer 102 from other epitaxial parts for forming a bipolar transistor, for example. p-type isolation region 114 is the epitaxial layer 1
115 is a gate electrode wiring.

Note that 104 and 105 are formed at the same time as the base emitter of a bipolar transistor (not shown), for example.
According to this embodiment, drains 106a-c are connected to P-WeI
Each drain 1 is formed so as to span llO3 and the epitaxial island region 102, and is electrically connected to each other by the epitaxial layer island region 102.
There is no need to take out the electrode wiring 110 from 06a-c.

In other words, as shown in FIG. 3, two contact parts for taking out the electrode wiring 110 only from the drain 106a are unnecessary in this embodiment compared to the structure shown in FIG. 2, and the area is reduced accordingly. Become. Normally, when making a contact for taking out an electrode, a few μ
A margin of about 10 μm is required, and a wiring portion up to the contact portion is also required, which requires a large area. Two source and drain regions in one J-FET.
When producing about 0 to 30 contacts, the reduction in the number of contacts will be of great benefit in manufacturing semiconductor integrated circuits. Furthermore, according to FIG.
6b and 106c facilitate the formation of source electrode wiring,
The installation location of the drain wiring 110 can also be made extremely small. Due to this actual situation, the J-FET shown in Figure 3
So, if the performance is the same in terms of Gml noise, etc., J- in Figure 2
It has become possible to reduce the area by 60 to 80% compared to FET. That is, according to FIG. 3, it is possible to significantly reduce the area occupied by the J-FET,
A great effect can be exhibited in semiconductor integrated circuits in which a large number of J-FETs are manufactured at once. Next, a J-FET according to another embodiment of the present invention will be explained with reference to FIG.

Reference numeral 116 is a p-type channel stopper region connected to the surface gate region 108.

The feature of this embodiment is that the front gate region 108 is mesh-shaped to reduce gate resistance. That is,
Further, in FIG. 4, 106d is provided as an n-type drain region, source regions 105c and 105d are provided, and a channel region 107e is also provided between the drain region 106b and the source region 105c, forming a channel in three directions of 106b. By making the channel width even longer, it is possible to increase Gm. 107f-h are additional channel areas.

In the example shown in FIG. 2, if the gate is made into a mesh shape, the source and drain wires will inevitably intersect, which increases the number of manufacturing steps and is extremely disadvantageous in terms of IC manufacturing.However, in the example shown in FIG. Since it can be formed under the wiring 109, the gate 108 can be formed into a mesh shape without increasing the number of manufacturing steps. Here, the advantage of forming the gate 08 in a mesh shape is that it not only increases the transfer conductance but also reduces the gate resistance. In other words, if the gate 108 is formed into a mesh shape, the resistance from the gate lead-out wiring section to the farthest gate position will be in the form of the gate resistances of the channels at each position being connected in parallel, and the gate resistance will be extremely reduced, as shown in Figure 3. Compared to this, thermal noise can be further reduced. In addition, in the example shown in FIG. 4, only the three directions of the source 105 and the drain 106 are configured to correspond to the gate 108, but if the number of the sources 105 and drains 106 is increased, the source 105 and the drain 106 can be 106
The four directions correspond to the gate 108, so that the transfer conductance can be increased with a small area, and this can be easily realized by the present invention. In the above embodiments, the surface gate 108 is provided on the channel 107, but the present invention does not necessarily require the gate 108.

However, by providing the gate 108, surface noise due to surface carriers flowing through the channel 107 can be reduced. Further, it goes without saying that 105 and 106 may be either the source or the drain. As described above, the present invention electrically connects either the source or the drain to each other in a region outside the gate island region, thereby reducing the number of contacts for taking out the electrode while still exhibiting the necessary performance. It has a great effect in reducing the integrated circuit area, and the gate can be made into a mesh shape with a simple structure, making a major contribution to the realization of high-performance, low-cost semiconductor integrated circuits including J-FETs. be.

[Brief explanation of drawings]

Figures 1a and 2a are schematic plan views of the main parts of a conventional J-FET, and Figures 1b and 2b are the same.
- V line, - sacrificial sectional view, Figures 3a and 4a are respectively schematic plan views of the main parts of the J-FET according to the embodiment of the present invention, Figures 3b and 4b are respectively -V, - is a sacrificial sectional view. 101...p-type silicon substrate, 102...
...N-type island region, 103...Pwell (back gate region), 105a-d...source region, 106a-d...drain region, 107a-
g...Surface gate region, 109...Source wiring, 110...Drain wiring, 111.
...Gate wiring.

Claims (1)

[Claims] 1. A gate region formed from the surface of an island region made of a semiconductor layer of one conductivity type formed on a semiconductor substrate and having a predetermined opening of the other conductivity type, and a gate region of the other conductivity type that straddles the opening. a first region formed from the surface of the gate region as shown in FIG.
a second region of the one conductivity type formed around the gate region and electrically connected to the first region by the island region; and a second region of the one conductivity type formed selectively within the gate region. a third region; and a channel region of the one conductivity type formed from the surface of the gate region from the third region between the first and second regions; 1. A semiconductor integrated circuit device comprising a junction field effect transistor in which one of the regions is a source and the other is a drain. 2. The semiconductor integrated circuit device according to claim 1, wherein the channel region is provided with a surface gate region of the other conductivity type connected to the gate region. 3. The semiconductor integrated circuit device according to claim 1, wherein the first, second and third regions are two-dimensionally arranged alternately, and the channel region is formed in a mesh shape.