JPS59175131A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS59175131A
JPS59175131A JP58049171A JP4917183A JPS59175131A JP S59175131 A JPS59175131 A JP S59175131A JP 58049171 A JP58049171 A JP 58049171A JP 4917183 A JP4917183 A JP 4917183A JP S59175131 A JPS59175131 A JP S59175131A
Authority
JP
Japan
Prior art keywords
substrate
control circuit
power transistor
solder
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58049171A
Other languages
Japanese (ja)
Inventor
Susumu Toba
鳥羽　進
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP58049171A priority Critical patent/JPS59175131A/en
Publication of JPS59175131A publication Critical patent/JPS59175131A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
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    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent the flowing out of solder material when a transistor substrate is mounted by a method wherein, when a control circuit substrate and a power transistor substrate are to be fixed on a common substrate, the transistor substrate is mounted at the recess part formed on the common substrate. CONSTITUTION:A recess part 12 and a rising part 13 are formed in the center part of a metal substrate 1, and a power transistor chip 2 is mounted in the recess part 12. To be more precise, the chip 2 mounted on an insulating substrate 5, through the intermediaries of a solder material, a metal block 3 and a solder material 4, is soldered on the bottom face of the recess part using a solder layer 7. On the other hand, a control circuit substrate 9 is attached to the rising part 13 using a bonding layer 10. According to this constitution, the flow out of solder material 7 onto a control circuit substrate part can be prevented when the insulating substrate 5 is mounted thereon.

Description

【発明の詳細な説明】 本発明は、例えば内燃機関点火装置用の混成集積回路の
ようにパワートランジスタチップ部および制御回路部を
それぞれ共通の金属基板上に塔載した混成集積回路に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit, such as a hybrid integrated circuit for an internal combustion engine ignition system, in which a power transistor chip section and a control circuit section are respectively mounted on a common metal substrate.

そのような混成集積回路においては、第一にパワートラ
ンジスタは金属基板よシ絶縁すること、第二にパワート
ランジスタの放熱をよくすること、第三にこの発熱が断
続的であるので熱サイクルに強い部品構成であること、
第四にできるだけ小形、軽量であること、第五に組立容
易であり製品として安価であることが要求される。これ
らの要求を満足するため通常共通の金属基板に、パワー
トランジスタチップを金属ブロックを介して支持する絶
縁基板を軟ろうまたは硬ろうによりろう付けし、その絶
縁基板にできるだけ近接させて上面に制御回路を形成し
た絶縁性の回路基板を接着した構造がとられている。し
かしパワートランジスタチップをろう付けする際、ろう
が側方へ流出するとろう層内に空孔が生じ十分な接合強
度が得られず、また回路基板まで流れて基板の側面また
は表面を覆って回路の短絡あるいは絶縁耐力の低下など
を生ずるおそれがある。In such a hybrid integrated circuit, firstly, the power transistor must be insulated from the metal substrate, secondly, the power transistor must have good heat dissipation, and thirdly, since this heat generation is intermittent, it must be resistant to thermal cycles. Must be composed of parts,
Fourthly, it must be as small and lightweight as possible, and fifthly, it must be easy to assemble and be inexpensive as a product. To meet these requirements, an insulating substrate that supports the power transistor chip via a metal block is usually soldered to a common metal substrate using soft or hard solder, and the control circuit is mounted on the top surface as close as possible to the insulating substrate. The structure is made by bonding an insulating circuit board formed with . However, when brazing power transistor chips, if the solder flows out to the side, pores are created in the solder layer, making it impossible to obtain sufficient bonding strength.In addition, the solder flows to the circuit board and covers the sides or surface of the board, causing damage to the circuit. There is a risk of short circuit or reduction of dielectric strength.

本発明はこの欠点を除き、パワートランジスタ部の健全
なろう付きができ、隣接制御回路部へろうの流出するこ
とのない混成集積回路を提供することを目的とする。It is an object of the present invention to eliminate this drawback and provide a hybrid integrated circuit in which the power transistor section can be soldered in a sound manner and the solder does not flow out to the adjacent control circuit section.

この目的は、パワートランジスタチップを金属ブロック
を介して支持する絶縁基板がその基板面よシやや大きい
寸法の底面をもっ凹部の底面にろう付けされることによ
って達成される。This object is achieved by brazing the insulating substrate, which supports the power transistor chip via the metal block, to the bottom surface of the recess, which has a bottom surface slightly larger than the substrate surface.

以下図を引用して本発明の実施例について説明する。第
１図および第２図において、金属基板１は両側に取付は
孔１１を有し、中央部には四部１２と隆起部１３が形成
されている。パワートランジ金属ブロック３には半導体
と熱膨張係数の近似したＭｏ　とＮｉ　　との合せ板、
あるいはＣｏ板等が用いられる。金属ブロック３は例え
ばＡ４２０．板の両面にＷメタライズを施こしその上に
Ｎｉ　めっきした絶縁基板５にはんだのような軟ろうあ
るいは銀ろうなどの硬ろうよりなるろう層６によりろう
付され、この絶縁基板５は上側のろう６と同等の軟ろう
あるいは硬ろうよりなるろう層７によって金属基板１の
凹部１２の底面にろう付されている。Embodiments of the present invention will be described below with reference to the drawings. In FIGS. 1 and 2, a metal substrate 1 has mounting holes 11 on both sides, and has four portions 12 and a raised portion 13 formed in the center. The power transistor metal block 3 includes a composite plate of Mo and Ni having similar thermal expansion coefficients to that of a semiconductor.
Alternatively, a Co plate or the like may be used. The metal block 3 is, for example, A420. An insulating substrate 5 with W metallization applied to both sides of the plate and Ni plating thereon is soldered with a brazing layer 6 made of soft solder such as solder or hard soldering such as silver solder. The solder layer 7 made of soft solder or hard solder similar to 6 is soldered to the bottom surface of the recess 12 of the metal substrate 1.

金属基板１はＦｅ　、　Ｃｕ　、　Ａｔ　　などの金属
にＮｉめっきを施したものあるいはこれらとエンジニア
リングプラスチックとの複合材料からなる。凹部１２の
底面はその周囲の基板１の面１４に対して０．１〜５．
０調の範囲でへこんでいる。凹部１２の底面の寸法は絶
縁基板５の面の寸法よりやや大きくされるが、その寸法
はチップ２、金属ブロック３、絶縁基板５の材質２寸法
あるいはろうの材質、量に応じて適当な値をとる。これ
により絶縁基板５をろう付けするろうが四部１２の外へ
流出することがなく、健全なろう付けに必要な量がその
Ａｔ保たれる。従ってろう層７には空孔等の欠陥が少な
く、パワートランジスタからの放熱が良好であり、熱サ
イクルにも強い接着が得られる。またとの凹部１２によ
り絶縁基板５の位置が自動的に決するため、組立てが容
易と々る。上面に制御回路を構成する各素子８を装着し
た例えば厚膜回路基板９は接着剤層１０によって金属基
板１の隆起部１３に接着され、トランジスタチップ２の
各電極と制御回路とは、例えば１００〜５００μｍの直
径のｋＡ線２１で接続される。パワートランジスタ部お
よび制御回路部は制御回路から引き出された端子２２が
貫通するそれぞれ絶縁性の端子枠２３と蓋２４とに包囲
される。端子枠２３を接着剤層２５により基板１と、蓋
２４は接着剤層２６により端子枠２３と接着することに
より混成集積回路ができ上がる。The metal substrate 1 is made of a metal such as Fe, Cu, At, etc. plated with Ni, or a composite material of these metals and engineering plastic. The bottom surface of the recess 12 is 0.1 to 5.
It is concave in the 0 tone range. The dimensions of the bottom surface of the recess 12 are made slightly larger than the dimensions of the surface of the insulating substrate 5, but the dimensions are set to appropriate values depending on the dimensions of the chip 2, the metal block 3, the materials of the insulating substrate 5, or the material and amount of the solder. Take. As a result, the solder used to braze the insulating substrate 5 does not flow out of the four parts 12, and the amount of At required for sound brazing is maintained. Therefore, the solder layer 7 has few defects such as holes, has good heat dissipation from the power transistor, and has strong adhesion that can withstand thermal cycles. Also, since the position of the insulating substrate 5 is automatically determined by the recess 12, assembly is easy. For example, a thick film circuit board 9 with elements 8 constituting a control circuit mounted on its upper surface is adhered to a raised part 13 of the metal substrate 1 by an adhesive layer 10, and each electrode of the transistor chip 2 and the control circuit are connected to each other, for example, by a layer of 100. It is connected by a kA wire 21 with a diameter of ~500 μm. The power transistor section and the control circuit section are surrounded by an insulating terminal frame 23 and a lid 24, respectively, through which terminals 22 drawn out from the control circuit pass. A hybrid integrated circuit is completed by bonding the terminal frame 23 to the substrate 1 using an adhesive layer 25 and the lid 24 to the terminal frame 23 using an adhesive layer 26.

制御回路基板９は上の実施例では基板１の隆起部１３に
接着されるが、この隆起部１３は面１４と同一面でもよ
い。この場合も絶縁基板５をろう付けするろうの量を適
当に選ぶことによりろうが制御回路基板に達することは
ない。いずれにしてもパワートランジスタチップ２が凹
部１２の底面に支持されるので、チップ２の上面の高さ
は低くなり、混成集積回路を薄形化することができる。Although the control circuit board 9 is glued to a raised portion 13 of the substrate 1 in the above embodiment, this raised portion 13 may be flush with the surface 14. In this case as well, by appropriately selecting the amount of solder used to braze the insulating board 5, the solder will not reach the control circuit board. In any case, since the power transistor chip 2 is supported on the bottom surface of the recess 12, the height of the top surface of the chip 2 is reduced, and the hybrid integrated circuit can be made thinner.

また上の実施例のような中空パッケージでなく樹脂モー
ルドパッケージを適用してもよい。Furthermore, a resin mold package may be used instead of the hollow package as in the above embodiment.

以上述べたように本発明は制御回路部に近接し同じ基板
上に塔載されるパワートランジスタ部の絶縁基板を基板
の凹部底面にろう付′けするものである。これにより、
パワートランジスタ部の正確な位置決め、健全なろう付
は及び隣接制御回路部への障害の阻止が保証され、背頭
に述べた５条件　５　− を満足する混成集積回路の信頼性が向上しコストも低下
するので、特に内燃機関点火装置用混成集積回路として
極めて有効に使用できる。As described above, in the present invention, the insulating substrate of the power transistor section, which is mounted on the same substrate in the vicinity of the control circuit section, is brazed to the bottom surface of the recess of the substrate. This results in
Accurate positioning of the power transistor section, sound brazing, and prevention of damage to the adjacent control circuit section are guaranteed, and the reliability of the hybrid integrated circuit that satisfies the 5 conditions 5- mentioned above is improved and costs are reduced. Therefore, it can be used extremely effectively especially as a hybrid integrated circuit for an internal combustion engine ignition system.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の蓋を除いての平面図、第２
図はその断面図である。 １・・・金属基板、２・・・パワートランジスタチップ
、３・・・金属ブロック、５・・・絶縁基板、７・・・
ろう層、９・・・制御回路基板、１２・・・凹部。 　６−Fig. 1 is a plan view of one embodiment of the present invention excluding the lid;
The figure is a sectional view thereof. DESCRIPTION OF SYMBOLS 1... Metal substrate, 2... Power transistor chip, 3... Metal block, 5... Insulating substrate, 7...
Brazing layer, 9... Control circuit board, 12... Recessed portion. 6-

Claims (1)

【特許請求の範囲】[Claims] 】）共通の金属基板に、パワートランジスタチップを金
属ブロックを介して支持する絶縁基板がろう付けされ、
該絶縁基板に近接して上面に制御回路を形成した絶縁性
の回路基板が接着されるものにおいて、パワートランジ
スタチップを支持する絶縁基板が該基板面よりやや大き
い寸法の底面をもつ凹部の底面にろう付けされたことを
特徴とする混成集積回路。]) An insulating substrate that supports the power transistor chip via a metal block is brazed to a common metal substrate.
In a device to which an insulating circuit board with a control circuit formed on the upper surface is adhered close to the insulating substrate, the insulating substrate supporting the power transistor chip is attached to the bottom surface of a recess having a bottom surface slightly larger than the substrate surface. A hybrid integrated circuit characterized by being soldered.
JP58049171A 1983-03-24 1983-03-24 Hybrid integrated circuit Pending JPS59175131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58049171A JPS59175131A (en) 1983-03-24 1983-03-24 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58049171A JPS59175131A (en) 1983-03-24 1983-03-24 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS59175131A true JPS59175131A (en) 1984-10-03

Family

ID=12823620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58049171A Pending JPS59175131A (en) 1983-03-24 1983-03-24 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS59175131A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61207038U (en) * 1985-06-14 1986-12-27
US5701033A (en) * 1995-03-20 1997-12-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741655B2 (en) * 1974-02-21 1982-09-04

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741655B2 (en) * 1974-02-21 1982-09-04

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61207038U (en) * 1985-06-14 1986-12-27
US5701033A (en) * 1995-03-20 1997-12-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

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