JPS59174953A - スキヤンイン／アウト制御方式 - Google Patents

スキヤンイン／アウト制御方式

Info

Publication number
JPS59174953A
JPS59174953A JP58049794A JP4979483A JPS59174953A JP S59174953 A JPS59174953 A JP S59174953A JP 58049794 A JP58049794 A JP 58049794A JP 4979483 A JP4979483 A JP 4979483A JP S59174953 A JPS59174953 A JP S59174953A
Authority
JP
Japan
Prior art keywords
scan
clock
clocks
control
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58049794A
Other languages
English (en)
Japanese (ja)
Other versions
JPS638498B2 (enrdf_load_stackoverflow
Inventor
Kiyoshi Sato
清 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58049794A priority Critical patent/JPS59174953A/ja
Publication of JPS59174953A publication Critical patent/JPS59174953A/ja
Publication of JPS638498B2 publication Critical patent/JPS638498B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP58049794A 1983-03-25 1983-03-25 スキヤンイン／アウト制御方式 Granted JPS59174953A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58049794A JPS59174953A (ja) 1983-03-25 1983-03-25 スキヤンイン／アウト制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58049794A JPS59174953A (ja) 1983-03-25 1983-03-25 スキヤンイン／アウト制御方式

Publications (2)

Publication Number Publication Date
JPS59174953A true JPS59174953A (ja) 1984-10-03
JPS638498B2 JPS638498B2 (enrdf_load_stackoverflow) 1988-02-23

Family

ID=12841054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58049794A Granted JPS59174953A (ja) 1983-03-25 1983-03-25 スキヤンイン／アウト制御方式

Country Status (1)

Country Link
JP (1) JPS59174953A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62236043A (ja) * 1986-03-31 1987-10-16 タンデム　コンピユ−タ−ズ　インコ−ポレ−テツド デ−タプロセツサテスト用のインライン走査制御装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62236043A (ja) * 1986-03-31 1987-10-16 タンデム　コンピユ−タ−ズ　インコ−ポレ−テツド デ−タプロセツサテスト用のインライン走査制御装置

Also Published As

Publication number Publication date
JPS638498B2 (enrdf_load_stackoverflow) 1988-02-23

Similar Documents

Publication Publication Date Title
JP2735034B2 (ja) クロック信号分配回路
GB1581864A (en) Logic systems
US7624209B1 (en) Method of and circuit for enabling variable latency data transfers
EP0273642B1 (en) Apparatus for reading data from memory
JP3197026B2 (ja) 遅延試験能力を有する走査可能なレジスタ
JPH0711787B2 (ja) デ−タ処理装置
JPS59174953A (ja) スキヤンイン／アウト制御方式
Molnar et al. Simple circuits that work for complicated reasons
GB1570336A (en) Fet circuits
JPS59211146A (ja) スキヤンイン方法
US6557157B1 (en) Method for designing complex digital and integrated circuits as well as a circuit structure
US6973422B1 (en) Method and apparatus for modeling and circuits with asynchronous behavior
JPH11108995A (ja) 関数クロック発生回路およびそれを用いたシフトレジスタ回路
Han et al. Clocked and asynchronous FIFO characterization and comparison
JPS5691534A (en) Array logic circuit
JP3278833B2 (ja) 論理回路テスト方法及びテスト入力回路及びテスト出力回路
EP0173257B1 (en) Integrated circuit device
JPS60124742A (ja) スキャン・イン・アウト制御方式
JP2820975B2 (ja) 大規模集積回路のスキャンテスト方法
JPH03216898A (ja) 集積回路
JP3166781B2 (ja) 加算回路
JP2543119B2 (ja) 論理回路のテスト方法
JP2771628B2 (ja) タイマカウンタ
JPH0736770A (ja) 半導体メモリ装置
CA1090000A (en) Ground station data storage system