JPS59172742A - Manufacture of semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To easily realize any kind of connection of CMOS circuit, TTL circuit and ECL circuit by forming P-MOS transitor, N-MOS transistor, bipolar transistor and diode which become basic elements in the particular format on a water. CONSTITUTION:First, a P-MOS transistor 1, an N-MOS transistor 2, a junction diode 3 which become basic elements and a baisic element A of junction type bipolar transistor 4 are formed on a wafer. These basic elements are wired into the circit, thereby forming any of the interface circuit B with TTL and the interface circuit C with ECL. Even when the disposition of basic elements is the same, the TTL interface and ECL interface circuits can be formed only in corresponding to the processes after the wiring and the master slice method can be employed.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a method of manufacturing a semiconductor logic circuit.

[Prior Art] With advances in semiconductor microtechnology, MOS circuits have rapidly increased in speed and are being used in a wide range of electronic devices. Particularly in digital devices such as electronic computers, it has become possible to use or replace conventional TTL1 circuits, E, and CL circuits. In this way, the cMOS circuit is wide (
(If used, an interface with the TTL circuit or ECL circuit is required.
Bi-c MOS circuits are known that use bipolar transistors to supplement the drive ability of MOS circuits. However, this has only been proposed as a speed-up of the cMO8 output circuit, or has been proposed for cMOS and TTL or ECL.
This is an interface circuit that is suitable only for a certain specific circuit, for example, a TTL circuit, in relation to output level matching and power supply voltage, and has been designed to be compatible with TTL circuits and ECL circuits.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a semiconductor fl* buried circuit that can easily accommodate the connection between a cMO8 circuit and either a TTLl path or an ECLl path.

[Essentials of the invention]

This @Akira has pMOS transistors and nM transistors on the wafer.
OS) A step of forming a transistor, a bipolar transistor, and a diode, configuring a cMOS inverter circuit with the pMO8) transistor and the pMO8) transistor, and forming a cMOS inverter circuit between the pMOS transistor of the inverter circuit and a high-level power supply terminal. The above diode and
Either the wiring connects the bipolar transistor whose base and collector are connected in series, or the pMO8) transistor and the nMOS transistor constitute a cMOS inverter circuit, and the inverter circuit's pMO8) transistor, the anode of the diode, and the bipolar transistor Select one of two wirings: connect the collector to the high-level power supply terminal, connect the output of the inverter circuit to the cathode of the diode and the base of the bipolar transistor, and connect the emitter of the bipolar transistor as the final output. The specialty of this paper is a method for manufacturing semiconductor logic circuits, which consists of the steps of wiring.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, as shown in FIG. 1, a basic element pMO8 (p channel Metal 0
xide Sem1conductor ) Transistor 1, n M O8 (n channel M
etal Oxide Sem1conducto
r) forming the basic elements of the transistor 2, the junction diode 8 and the junction bipolar transistor 4;

These basic confections can be connected to the circuit shown in Figure 2 or the circuit shown in Figure 8.
Wire to either of the circuits shown in the figure and connect the TTL shown in Figure 2.
An interface circuit with the ECL shown in FIG. 8 is configured.

According to this, by employing the master slice method, it is possible to configure either a TTL or ECL interface circuit using the same basic element.

Referring to Figure 2, pMO, s) gingista l and nM
OS) The transistor 2 constitutes a cM, OS inverter circuit. A junction diode 8 and a diode-connected bipolar transistor 4 whose base and collector are connected are connected in series between the pMOS transistor 1 of this inverter circuit and a high-level power supply terminal vDD. nMOS
) The transistor 2 is connected to the low power supply terminal vss.

According to the circuit shown in Figure 2, when the input IN is at low level, pM
O8) The transistor 1 is turned on and the output OUT becomes high level. Conversely, when IN is at high level, nMOS transistor 2 is turned on and OUT is at the 4-level. cMOs
The voltage of the high-level power supply to the inverter circuit is the voltage B VBK due to diode 8 and transistor 4; 1.5 V
only becomes lower. When VDD and vss are set to the same value as the power supply voltage of the TTL circuit, VDD-5V, vs, = Ov, the output high level of the power output and OUT becomes 3.5 V, and the output low level becomes Ov. According to the circuit of FIG. 2, by connecting the diode 8 and the transistor 4 to the high power supply side of the CMOS inverter circuit using the same value as the power supply voltage of the TTL circuit, the conventional VDD can be connected to the MOS A high level of improvement is achieved compared to the case of direct connection. The signal amplitude becomes an appropriate value of approximately 3.5 V, and compared to the case of 5 V, it can be seen that not only the transient response (current change noise and coupling noise) is reduced. The thing is that the Xν10S device is miniaturized ((with this comes the problem of a drop in breakdown voltage. In the circuit shown in Figure 2, vDD is used at the conventional 5V, and the element breakdown voltage is only 3.5V, so it is extremely It's advantageous.

Referring to FIG. 8, similarly to FIG. 2, a pMOS transistor 1 and an nMOS transistor 2 constitute a cMOS inverter circuit. This pMO8) transistor 1 is connected to the high-level t-line terminal vDD, and the nMOS transistor 2 is connected to the low-level '#t# terminal vssFc.

Furthermore, the collector of the piebola transistor 4 is connected to the higher power supply terminal VDD, the output of the CMOS inverter circuit is connected to the base of the bipolar transistor 40, the emitter is connected to the output terminal OUT, and the emitter of the transistor 4 outputs an ECL level. ”. Furthermore, a diode 8 is connected between the high-level wire terminal vDD and the base of the bipolar transistor 4 to clamp the low level.

According to the circuit shown in FIG. 8, when input I-N is at low level, p
When the MOS transistor 1 is turned on and the output of the cMOS inverter circuit becomes high level, the bipolar transistor circuit is also turned on, and the output OUT becomes high level. Conversely, when the input IN is at a high level, the 11M0S transistor 2 is turned on, the output of the CMOS inverter circuit is at a low level, the bipolar transistor circuit is turned off, and the output OUT is at a low level. For this circuit, VDD=Ov1v, 5--2v and normal (7,) ECL
A terminating resistor "TT" of times M can be used. Therefore, °
Unlike the case of rTL, there is no problem with voltage resistance.

In this way, even if the layout of the basic elements is the same as shown in Figure 1, the TTI, interface 1, and ECL interface circuits can be changed just by taking steps after the wiring process.
J ability and can adopt master slice techniques. In addition, in the TTL interface circuit shown in FIG. 2, which has a 2" comb, even if a normal 5V power supply is used, there is no breakdown voltage bottleneck, and it is possible to advance miniaturization.

FIG. 4 is a modification of FIG. 2, and the basic operation is the same as that in FIG. 2.

[Efficacy of invention]

Due to non-invention, cMOS circuit and T'I'L
Easily compatible with both circuits and ECL circuits:
i- can do it.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a basic element configuration according to an embodiment of the invention, FIG. 2 is a diagram showing a TTL intern eighth circuit using the basic elements shown in FIG. 1, and FIG. 8 is a diagram showing an E
A diagram showing the CL interface circuit, Figure 4 is the second
It is a figure which shows the modification of a figure. 1... pMOS transistor, 2... nMO8) transistor, 8... diode, 4... bipolar transistor. ■DD ss

Claims (1)

[Claims] +1) pMOS transistor and nM transistor on wafer
forming an OS transistor, a bipolar transistor, and a diode, and the above pMO8)
A cMOS inverter circuit is configured with a transistor and nMO8) The transistor is connected in series with the bipolar transistor and the diode to obtain a voltage drop phase between the two, which is connected to the inverter circuit to match the T'rL level. Either the wiring or the above pMOS transistor and nMO8) transistor, the C bipolar transistor operates as an emitter follower where the amplitude is limited and clamped by the above diode, and select either one of the wirings to be connected to the above inverter circuit so as to match the ECL level. A method for manufacturing a semiconductor logic circuit, which comprises a step of performing wiring.