JPH01260692A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of the developing processes of a dynamic RAM or the like adapted to plural interface conditions by providing plural input circuits and/or output circuits selectively made effective according to the level of an input signal and/or output signal. CONSTITUTION:For instance, in a semiconductor integrated circuit device such as the dynamic type RAM, plural input circuits ETC, TIC and the output circuits EOC, TOC capable being adapted to a ECL (Emitter Coupled Logic) interface and a TTL (Transistor Transistor Logic) interface respectively are disposed and made selectively effective by a master slice according to the level of the input signal and the output signal. Accordingly, the semiconductor integrated circuit device of the ECL interface and the TTL interface can be simultaneously designed and developed. Thereby, the number of the development processes of the semiconductor integrated circuit device adapted to the plural interfaces as mentioned above can be reduced to attain the low cost thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, such as a dynamic RAM (Random A-cc).
The present invention relates to a technique that is particularly effective when used in applications such as ESSMemory.

[Conventional technology]

The memory cell is a MOSFET (Metal 0xi
-de Sem1conductor Field
There are dynamic type RAM' and static type RAM configured by effect transistors. In addition, the memory cell is bipolar R formed by a bipolar transistor.
There is AM. Dynamic RAM is characterized by low power consumption and high degree of integration of circuit elements, and bipolar RAM is characterized by high-speed operation. The characteristics of static RAM are located between those of dynamic RAM and bipolar RAM.

On the other hand, by replacing the input/output circuit of static RAM with a bipolar/0MO3 (complementary MO3) complex logic circuit, bipolar RAM achieves high-speed operation comparable to bipolar RAM, low power consumption, and elevated stacking capacity comparable to static RAM. -CMO3 type RAM has been proposed. Bipolar CMOS type RAM is suitable for high-speed systems.
CL (Emitter Coupled Log
ic) has an interface and input/output signal ECL-M
It has a built-in level conversion circuit that performs OS level conversion.

For bipolar CMO3 type RAM, for example, 1
It is described in "Nikkei Electronics" published by Nikkei McGraw-Hill, March 10, 1986, pages 199 to 217.

[Problem to be solved by the invention]

Prior to the present invention, the inventors of the present application developed a dynamic RAM having an ECL interface similar to the bipolar CMO3 RAM described above. This dynamic RAM constitutes a low-speed, large-capacity storage device in the storage hierarchy of a high-speed system.

By the way, dynamic RAM is TTL (Tra
Transistor Logic)
It is also used in low-speed systems that have an interface.

For this reason, the inventors of the present application developed a TT which has the same internal structure as the ECL ink face dynamic RAM.
We decided to develop a dynamic RAM with L interface. However, dynamic type RAM with ECL interface and dynamic type R with TTL interface
Separately designing and developing AM increases the number of development steps, which becomes a factor that hinders product cost reduction.

An object of the present invention is to reduce the number of man-hours required to develop a dynamic RAM or the like that can meet a plurality of interface conditions. Another object of the present invention is to reduce the cost of a semiconductor integrated circuit device that can meet a plurality of interface conditions.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

(Means for Solving the Problems) A brief overview of typical inventions disclosed in this application is as follows.

That is, a semiconductor integrated circuit device such as a dynamic RAM is provided with a plurality of input circuits and output circuits that can be adapted to each of an ECL interface and a TTL interface, and these input circuits and output circuits are connected to input signals and output circuits by a master slice. It is selectively enabled according to the level of the output signal.

[For production]

According to the above means, the ECL interface and the TT
Simultaneously design L-interface semiconductor integrated circuit devices,
Therefore, it is possible to reduce the number of steps required to develop a semiconductor integrated circuit device that is compatible with such a plurality of interfaces, and to reduce the cost thereof.

(Example) FIG. 2 shows a dynamic RA to which this invention is applied.
A block diagram of one embodiment of M is shown. The circuit elements constituting each circuit block in the figure are formed on a single semiconductor substrate such as single-crystal silicon, although not particularly limited, by known semiconductor integrated circuit manufacturing techniques.

The dynamic RAM of this embodiment is compatible with both an ECL interface and a TTL interface, although this is not particularly limited. Therefore, a timing generation circuit TG that receives control signals, an address multiplexer AMX and a column address sofa CAB that receive address signals, and a data input/output circuit I10 that inputs and outputs stored data.
etc., the ECL interface and T
A plurality of input circuits and output circuits are provided corresponding to each of the TL interfaces. Although not particularly limited, these input circuits and output circuits are made selectively effective by selectively forming predetermined connection wiring by the master slice.

Further, the dynamic RAM of this embodiment is designed to have the same arrangement of input/output terminals as that of a conventional static RAM, so that it has a so-called pseudo-static RAM configuration. Therefore, the row address, that is, the X address signals AXO to AXi, and the column address, that is, the Y address signals AYO to AYj, are inputted through separate external terminals. The dynamic RAM also has a chimbu enable signal G as a control signal.
E. Write enable signal WE and output enable signal plane 5 (supplied. Although not particularly limited, a dynamic RAM has a function of performing a refresh operation of stored data in accordance with a refresh control signal RF.

In FIG. 2, the dynamic RAM consists of two sets of memory arrays MARYO and MARYI arranged symmetrically.
, sense amplifiers 5APO, 5API, 5ANO, 5ANI, and column switches C3O and C3I provided corresponding to these memory arrays.

Memory arrays MARYO and MARYI have m+1 word lines arranged vertically in the figure, n+1 sets of complementary data lines arranged horizontally, and a grid at the intersections of these word lines and complementary data lines. (m+
1) X (n+1) dynamic memory cells.

Word lines constituting memory arrays MARYO and MARYI are connected to corresponding row address decoders RADO and R.
It is coupled to ADI and is alternatively set in the selected state.

A predetermined predecode signal is supplied from the row address decoder PRAD to the row address decoders RADO and RAD1. Row address decoders RADO and RADl selectively set the corresponding word line of memory array MARYO or MARYII to a selected state of the λ low level according to these predecode signals.

Although not particularly limited, the low address decoder PRAD receives i-bit complementary internal address signals axQ to axi excluding the most significant bit from the row address buffer RAB.
-1 (here, for example, the non-inverted internal address signal axO and the inverted internal address signal axQ are collectively expressed as a complementary internal address signal axQ; the same applies hereinafter) is supplied.

Further, a timing signal φX is supplied from a timing generation circuit TG, which will be described later. Brillou address decoder PR
The AD is selectively brought into operation when the timing signal φX is set to a high level.

In this operating state, the Brillou address decoder PR
AD is the complementary internal address signal axQ to axi-1.
are decoded in a predetermined combination to form the predecoded signal and supply it to the row address decoder RAD.

Row address buffer RAB holds row address signals supplied via address multiplexer AMX, and forms the complementary internal address signals axO to axi based on these row address signals.

One input terminal of the address multiplexer AMX has
An i11-bit X address signal AXO-AXi is supplied via external terminals AXO-AXi, and refresh address signals arQ-ari are supplied from a refresh address counter RFC to the other input terminal.

Address multiplexer AMX is further supplied with timing signal φref from timing generation circuit TG.

This timing signal φref is applied to the dynamic RAM.
When in refresh mode, it is selectively set to high level. Address multiplexer AMX selects the X address signals AXO to AXi when timing signal φref is set to low level, and transmits the selected X address signals AXO to AXi as row address signals to row address buffer RAB. Also,
When the timing signal φref is set to high level, the refresh address signals arQ to ari are selected;
It is transmitted to the row address buffer RAB as a row address signal.

The address multiplexer AMX has i,01 pairs of ECLs provided corresponding to the X address signals AXO to AXi.
Contains an input circuit and a TTL input circuit. Although not particularly limited, each pair of ECL input circuit and TTL input circuit is selectively enabled by having predetermined connection wiring selectively formed by the master slice.

The refresh address counter RFC performs a step operation in accordance with the timing signal φre supplied from the timing generation circuit TG, and
Form Q-ari.

On the other hand, complementary data lines constituting memory arrays MARYO and MARYI are coupled at one end to corresponding unit circuits of corresponding sense amplifiers SAP O and SAP 1. On the other hand, the corresponding column switches C3O and C5I are coupled to the corresponding unit circuits of the corresponding sense amplifiers 5ANO and 5AN1.
are coupled to corresponding unit circuits.

Sense amplifiers 5APO and SAP1 include n+1 unit circuits provided corresponding to each complementary data line of memory arrays MARYO and MARYI. Each unit circuit is
Each includes a pair of P-channel inter-channel O3FETs provided between the common source line sp and each complementary data line. These P-channel O3 FETs have their gates and drains cross-connected to each other. In addition, the common source line SP
, a drive M is selectively turned on according to a timing signal φpa supplied from a timing generation circuit TG.
The power supply voltage Vcc of the circuit is selectively supplied via the O3FET.

Similarly, sense amplifiers 5ANO and 5ANI include fi'+1 unit circuits provided corresponding to memory arrays MARYO and MARYI. Each unit circuit includes a pair of N-channel MOS FETs provided between the common source line SN and each complementary data line. These N-channel MO3FETs have their gates and drains cross-connected to each other. Further, the common source line SN is selectively supplied with the ground potential of the circuit via another drive MO3FET that is selectively turned on according to the timing signal φpa supplied from the timing generation circuit TG.

Thereby, each unit circuit of sense amplifiers 5APO and 5AP1 and corresponding unit circuits of sense amplifiers 5ANO and 5ANI constitute one unit amplifier circuit.

These unit amplifier circuits are selectively brought into operation when the timing signal φpa is set to a high level. In this operating state, each unit amplifier circuit receives minute read signals output from the n+1 memory cells coupled to the selected word lines of the memory arrays M ARY O and MARY I via the corresponding complementary data lines. It is amplified and made into a high level or low level binary read signal.

Column switches C8O and C3I include, although not particularly limited to, n+1 unit circuits provided corresponding to each complementary data line of memory arrays MARYO and MARYl. These unit circuits are connected to the ground potential of the circuit and the read complementary common data "00L", RIOIL or Engineering R Engineering 100
R, RIOIR (here, for example, non-inverted signal line R100
Two pairs of N-channel MOSFs are provided in series between L and the inverted signal line 117 (also expressed as a read complementary common data line R100L (the same applies hereinafter).
Including ET. Among them, one pair of N-channel MO3FE
T has its gates connected to memory arrays MARYO and MAR
By being coupled to the node inversion signal line and the inversion signal line of the corresponding complementary data line of YI, the amplification MO3FET
functions as Also, another pair of N-channel MO3
The gates of the FETs are commonly coupled to the gates of another pair of N-channel MOS FETs in adjacent unit circuits, and corresponding read data line selection signals YRO, YR2 to YRn-1 are supplied from the column address decoder CAD, respectively. By doing so, it functions as a switch MO3FET. As a result, each complementary data line of memory arrays MARYO and MARYI is connected to the Guinaminok type RA
When M is in the read mode and the corresponding read data line selection signals YRO, YR2 to YRn-1 are alternatively set to high level, two sets are selected at a time. 101L or shaku 1
00R.

Selectively connected to RIOIR.

Each unit circuit of the column switches C8O and C8l is further connected to each complementary data line of the memory arrays MARYO and MARYl and the write complementary common data line 100L, WIOI.
It includes a pair of N-channel MO3FETs provided between L or WlooR and WIOIR. These N-channel MO3FETs have their gates commonly coupled to the gates of similar N-channel MO5FETs in adjacent unit circuits, and are supplied with corresponding write data line selection signals YWO, YW2 to YWn-1, respectively, from the column address decoder CAD. By doing so, it functions as a switch MO3FET. As a result, each complementary data line of memory arrays MARYO and MARYI is
is in the write mode and the corresponding write data line selection signals YWO, YW2 to YWn-1 are alternatively set to high level, so that two sets are selected at a time, and the write complementary common data lines W100L, WIOIL or WlooR are selected.
, WIOIH.

In other words, in the Guinamisoku type RAM of this embodiment, two sets of complementary common data lines for reading and two sets of complementary common data lines for writing are separately provided, and the memory array MARY
Two sets of O and MARYI complementary data lines are each selected and selectively connected to a complementary common data line for reading or writing. At this time, the complementary common data line for writing is directly coupled to the selected complementary data line via the corresponding unit circuit of column switch C8O or C3I. However, the complementary common data line for reading is indirectly coupled through the gate of the amplifying MO3FET of the corresponding unit circuit of column switch C8O or C5I. As a result, the signal amplitude of the complementary common data line for reading is reduced, and the speed of the reading operation is increased.

Each unit circuit of column switches C3O and C81 includes, but is not particularly limited to, a precharge circuit. These precharge circuits are selectively activated in accordance with timing signal φpc supplied from timing generation circuit TG, and set the corresponding complementary data lines of memory arrays MARYO and MARYI to half precharge level.

A predetermined predecode signal is supplied to the column address decoder CAD from the column address decoder PCAD. The column address decoder CAD selectively sets the read data line selection signals YRO, YR2 to YRn-1 or the write data line selection signals YWO, YW2 to YWn-1 to a high level selection state according to these predecode signals. do.

The column address decoder PCAD includes, but is not particularly limited to, a j-bit complementary internal address signal a y O excluding the most significant bit from the column address buffer CAB.
-a yj-1 is supplied, and the timing signal φy is supplied from the timing generation circuit TG. The virtual column address decoder PCAD is selectively put into an operating state when the timing signal φy is set to a high level. In this operating state, the Bricolumn address decoder PC
AD is the complementary internal address signal ayO-ayj-1
are decoded in a predetermined combination to form the predecoded signal and supply it to the column address decoder CAD.

Column address buffer CAB is connected to external terminal AYO-A.
It holds the j+1 bit Y address signals AYO to AYj supplied via Yj, and forms the complementary internal address signal ayQ-yj based on these Y address signals.

The column address buffer CAB has 11 pairs of ECLs provided corresponding to the Y address signals AYO-Ayj.
Contains an input circuit and a TTL input circuit. Each pair of ECL input circuit and TTL input circuit is connected by selectively forming corresponding predetermined connection wiring by a master slice.
Each is selectively valid.

Read complementary common data lines R100L and R100R and write complementary common data lines W100L and Wlo
oR is coupled to main amplifier MAO. Similarly, the read complementary common data line λ10 ], L and RIOI
R and write complementary common data lines WIOIL and W
IOIR is coupled to main amplifier MAL.

The main amplifiers MAO and MAL each include, but are not limited to, 21 read amplifiers and write amplifiers. Among these, the input terminals of each read amplifier of the main amplifier MAO are coupled to read complementary common data lines R100L and R100R, respectively, and the output terminals are connected to the data input/output circuit I1 via a common complementary output signal line moQ.
Combined with 0. Similarly, the input terminal of each read amplifier of the main amplifier MAL is connected to the read complementary common data line λl.
0LL and RIOIR, respectively, and its output terminal is coupled to the data input/output circuit I10 via a common complementary output signal line Uo1. - Main amplifier MAO
The output signal wm of the data input/output circuit I/'0 is commonly supplied to the input terminals of the write amplifiers of MAL and MAL.

The output terminal of each write amplifier of main amplifier MAO is connected to the corresponding write complementary common data line W100L and Wlo.
oR, and the output terminals of each write amplifier of the main amplifier MAL are respectively coupled to the corresponding write complementary common data line 101L and stem l01R.

The two lead amplifiers provided in each of the main amplifiers MAO and MAL are commonly supplied with the timing signal φra from the timing generation circuit TG, although this is not particularly limited. These read amplifiers are connected to the above timing signal φra.
When C is set to high level, column address buffer C
It is selectively brought into operation according to the complementary internal address signal axi of the most significant bit supplied from AB. In other words,
When the complementary internal address signal axi is set to logic "0", the read complementary common data line j
The read amplifier coupled to oOL and -RIOIL is activated, and the complementary internal address signal axi is set to logic "1".
”, the read complementary common data line unit 100R
and the read amplifier coupled to RIOIR are put into operation. In this operating state, each read amplifier further amplifies the binary read signal output from the selected memory cell of the memory arrays MARYO and MARYI via the corresponding read complementary common data line, and sends the signal to the data input/output circuit I10. introduce.

On the other hand, two write amplifiers provided in each of the main amplifiers MAO and MAL are commonly supplied with the timing signal φwa from the timing generation circuit TG, although this is not particularly limited. When the timing signal φwa is set to a high level, these write amplifiers, like the read amplifier, are selectively put into an operating state according to the complementary internal address signal axi of the most significant bit supplied from the column address buffer CAB. be done. In this operating state, each write amplifier receives the output signal wm of the data input/output circuit T10.
A complementary write signal is formed according to the following.

These complementary write signals are sent to memory arrays MARYO and MA through corresponding write complementary common data lines.
The signal is transmitted to the selected memory cell of RYI.

Although not particularly limited, the data input/output circuit I10 is an EC
ECL input circuit EIC and ECL output circuit EOC provided corresponding to the L interface, and TTL input circuits Tic and T provided corresponding to the TTL interface.
Includes TL output circuit TOC. Also, the complementary output signal line −μ
It includes an output selection circuit O3L that selectively transmits the read signal outputted through mOO and O1 to the ECL input circuit EIC or TTL input low circuit TIC. Of these, ECL input circuit EIC, TTL input circuit TIC, ECL output circuit EOC, and TTL output circuit TOC.
As will be described later, predetermined connection wiring is selectively formed by the master slice, so that it is selectively enabled.

ECL input circuits EIC and ' of data input/output circuit I10
The I'TL input circuit TIC is a dynamic type R'A
When M is in the write mode, the ECL level or TTL level write data supplied via the data input/output terminal DI○ is level-converted into a MOS level write signal. These write signals are sent to the main amplifier MA as the output signal wm of the data input/output circuit I10.
Commonly supplied to the O and MAI amplifiers.

On the other hand, the output selection circuit O3L of the data input/output circuit I10 is supplied with the most significant complementary internal address signal ayj from the above-described row address buffer RAB. The output selection circuit O3L converts the read signals output from the main amplifier MAO and the read amplifier of MAL via the complementary output signal lines moQ and mol into the complementary internal address signal ayj.
and transmits it to the ECL input circuit EIC or the TTL input circuit TIC.

ECL output circuit E○C and T of data input/output circuit I10
The T L output circuit TOC is selectively brought into operation when the timing signal φoe supplied from the timing generation circuit TG is set to a high level. In this operating state, the ECL output circuit EOC and the TTL output circuit TO
C sends out the read signal outputted via the output selection circuit O3L from the data input/output terminal DIO. When the timing signal φOe is set to low level, E
The outputs of the CL output circuit EOC and the TTL output circuit TOC are placed in a high impedance state.

The specific configuration and operation of the data input/output circuits ■/○ will be explained in detail later.

The timing generation circuit TG generates the above-mentioned various timing signals based on the chip enable signal -σ lower, the write enable signal W, the output enable signal, and the refresh control signal clove, which are supplied as control signals from the outside. and supplies it to each circuit of the dynamic RAM.

The timing generation circuit TG includes four pairs of ECL input circuits and TT provided corresponding to each of the above control signals. , each including an input circuit. Each pair of ECL input circuit and TTL
The input circuits are selectively enabled by selectively forming predetermined connection wires by the master slice.

FIG. 1 shows a circuit diagram of an embodiment of the data input/output circuit ■/○ of the dynamic RAM shown in FIG. In the figure, a MOSFET with an arrow added to the channel (back gate) portion is a P-channel type, and is displayed to be distinguished from an N-channel MOSFET without an arrow added. Also, all of the illustrated bipolar transistors are of the NP type.

The data input/output circuit I10 of this embodiment includes an ECL input circuit EIC and an ECL output circuit EOC provided corresponding to an ECL interface, and a TTL input circuit 'I' I C and T provided corresponding to a TTL interface.
Includes TL output circuit TOC.

As mentioned above, in the dynamic RAM of this embodiment, the address multiplexer AMX, the column address sofa CAB, and the timing generation circuit TG also have similar E
A CL input circuit and an ECL output circuit as well as a TTL input circuit and an 'FTL output circuit are provided, respectively. These input circuits and output circuits are connected by selectively forming corresponding predetermined connection wiring by the master slice.
Each is selectively valid.

In FIG. 1, a data input/output terminal DIO through which stored data is input/output is connected to an input terminal of a TTL input circuit TIC and an output terminal of a TTL output circuit TOC via a connection switching unit SCI, although this is not particularly limited. It is also coupled to the input terminal of the ECL input circuit E1C and the output terminal of the ECL output circuit EOC. Connection switching section S
Similar to other connection switching units described later, C1 selectively realizes two types of connection paths shown by solid lines or dotted lines by selectively forming its connection wiring using a master slice. This connection wiring is formed of an aluminum layer, although it is not particularly limited. In each connection switching section of this embodiment, connection wiring shown by a solid line is formed, and the dynamic RAM has a TTL interface. In each connection switching section, when the connection wiring shown by the dotted line is formed, the dynamic RAM
It is considered an interface.

The input terminal of the TTL input circuit TIC is coupled to the input terminal of the CMQ S inverter circuit N1. The output signal of the inverter circuit N1 is supplied to the input terminal of the bipolar CMOS inverter circuit BCNI. Bipolar CM
The OS inverter circuit BCNI is a normal bipolar CMOS impark circuit including two output hyperpolar transistors in a totem pole configuration.

1゛TL supplied via data input/output terminal I)10
The level write data is determined by the logic threshold of the impark circuit N1 of the TTL input circuit TIC, and converted into an inverted MOS level signal that sets the circuit power supply voltage Vcc to high I/bell and the circuit ground potential to low level. Ru. The output signal of the inverter circuit N1 is
Bipolar/CMOS inverter circuit] It is further inverted by 3CN1 to speed up the level change and increase the fanout. Bipolar CMO
The output signal of the S inverter circuit BCNI is the TTL input input circuit Ti quantity signal idt, and the output signal of the S inverter circuit BCNI is the TTL input input circuit Ti quantity signal idt.
2, and then the output signal w of the data input/output circuit I10.
m is output to the above-mentioned main amplifiers MAO and MAL.

By the way, bipolar CMOS inverter circuit BCN
The signal amplitude of the output signal I, that is, the output signal idt of the TTL input circuit TIC, is reduced by the base-emitter voltage of the output transistor constituting the bipolar CMOS inverter circuit BCNI. Therefore, although not particularly limited, the CM
A level correction circuit consisting of OS inverter circuits N4 and N5 is provided. The output signal idt of the TTL input circuit Tic is the output signal Wrr of the data input/output circuit I10.
The inverter circuit N
4 and N5, and its level becomes a full-swing MOS level signal that causes the circuit's power supply voltage Vcc to be at a high level and the circuit's ground potential to be at a low level.

On the other hand, the input terminal of the ECL input circuit EIC is coupled to the base of the transistor TI. The transistor 1'1 is
Its collector is coupled to the power supply voltage Vcc of the circuit, and its emitter is coupled to the ground potential of the circuit via a current source, thereby forming an input limiter follower circuit. The output signal of this input limiter follower circuit is the transistor T
It is transmitted to the base of 2.

The 1-transistor 1-2 has a differential configuration with the 1-transistor T3, which receives the reference potential Vr at its base.

Thereby, the transistors T2 and T3 constitute a current switch circuit that uses the reference potential Vr as a logic threshold. Needless to say, one of the i-ransistors T3
- The reference potential Vr supplied to the transistor T1 varies from the intermediate potential between the ECL level high level and low level.
is set to the value minus the base-emitter voltage of

The complementary output signal of the current switch circuit is 1-transistor T
Bipolar CMOS inverter circuit BCN2 is connected via an output limiter follower circuit whose basic configuration is
supplied to Bipolar/CMOS inverter circuit B
CN2 is an N-channel MOSFET with output transistors T6 and 1'7 in totem pole configuration.
Two current mirrors whose basic configuration is TQ 7 and Q8,
circuit. These current mirror circuits are MOS
By supplying the reference potential Vgl to the gates of the FETs Q7 and Q8, a predetermined logic threshold is provided for determining the output signal level of the current switch circuit. Thereby, the complementary output signal of the current switch circuit is converted to a MOS level by the bipolar CMOS inverter circuit BCN2.

The output signal of the bipolar CMOS inverter circuit BCN2 is used as the output signal ide of the ECL input circuit EIC.
It is output via the connection switching section SC2 described above.

Next, complementary output signals moQ 17 and mol 1 are output from the main amplifier MAO and the lead amplifier of MAL.
mol is the transistors T16 and T15 and T13 and T that constitute the corresponding differential amplifier circuit of the output selection circuit OSL.
12 bases each. The commonly coupled emitters of the differential transistors T16, T15 and T13, T12 are provided with transistors T17 and T14, respectively, which constitute a current source. These transistors T
A predetermined constant voltage Vcl is selectively supplied to the bases of 17 and T14 via N-channel type transmission gates MO3FETQIO and Q9, which are selectively turned on according to the complementary internal address signal ayj of the most significant bit. be done.

From these facts, when complementary internal address signal ayj is logic "0", MO3FETQ of output selection circuit O3L
IO is turned on, and the differential transistors T16 and T
15 is in the operating state. Therefore, the main amplifier M
Complementary output signal m o Q・m o output from AO
Q is transmitted through an output limiter follower circuit consisting of differential transistors T16 and T15 and transistors T19 and T18. On the other hand, when complementary internal address signal ayj is set to logic "1", MO3FETQ9 is turned on and differential transistors T13 and T12 are put into operation. Therefore, the complementary output signal mol-m01 output from the main amplifier MAI is transmitted via the output limiter follower circuit including the differential transistors Tl3 and T12 and the transistors TI9 and TlB.

When the dynamic RAM is a TTL interface, the complementary output signal 5t-st of the output selection circuit O3L is sent to the TTL output circuit TOC via the connection switching unit SC3.
supplied to When the dynamic RAM is an ECL interface, the complementary output signal of the output selection circuit O3L is further level-shifted by the diodes D2 and Dl, and is then outputted as the complementary output signal se-dτ via the connection switching unit SC3. It is supplied to the ECL output circuit EOC.

Although not particularly limited, the TTL output circuit TOC receives two complementary output signals 5t-s from the output selection circuit O3L.
CMOS inverter circuits N2 and N3. These inverter circuits each include N-channel MO5FETs Q5 and Q6 that receive reference potential Vg2 at their gates, so that they have a predetermined logic threshold with respect to the complementary output signal 5t-st.

The output signals of the inverter circuits N2 and N3 are supplied to one input terminal of the bipolar CMOS Nant gate circuits BCGI and BCG2. These bipolar commercials
The above-mentioned timing signal φOe is supplied from the timing generation circuit TG to the other input terminals of the OS NAND game 1 to circuit. Bipolar CMOS Nant gate circuit BC
The output signal of GI is supplied to the gate of N-channel type output MO3FBTQ3 via CMOS inverter circuit N7. In addition, the delay circuit DLI and the NOR gate circuit N
N-channel type output MO3FETQI via 0G1
is supplied to the gate. Here, the output MO5FETQI
has a relatively large conductance, and the output MO3
FETQ3 is designed to have a small conductance compared to the output MO3FETQI. As a result, the output signal of the bipolar CMOS Nant gate circuit BCGI is output from an output MO with a relatively small conductance.
It is sent out at high speed via the 3FBTQ3, and after being delayed by the delay time of the delay circuit DLL, it is sent out via the output MOS FBTQ1 having a relatively large conductance. By sending read data in two stages in this way, it is possible to suppress current changes during data output and to suppress noise.

Similarly, bipolar CMOS Nant gate circuit BCG
The output signal No. 2 is supplied to the gate of an N-channel type output MO3FETQ4 via a CMOS inverter circuit N8. In addition, the delay circuit DL2 and the Nant gate circuit N
N-channel type output MO3FETQ via AGI etc.
2 gates. Here, the output MO3FETQ
2 has a relatively large conductance, and the output MO3F
E T Q 4 is designed to have a small conductance compared to the output MO5FET Q2.

As a result, bipolar CMOS Nant gate circuit B
The output signal of CG2 is sent to two stages via output MO3FETs Q4 and Q2.

On the other hand, although the ECL output circuit EOC is not particularly limited,
It includes at its base differential transistors T9 and TIO which receive the level-shifted complementary output signal 5e-se of the output selection circuit O3L. In this embodiment, the dynamic RAM is of the 100K type, and the differential transistors T9 and T10 constitute a predetermined amplifier circuit suitable for the 100K type. The non-inverted output signal of this amplifier circuit is P
It is supplied to the base of the output transistor Tll via the channel type transmission gate MO3FETQ22. M.O.
The gate of the 3FET Q22 is connected to the CMOS inverter circuit N for the timing signal φoe, although it is not particularly limited.
6 is supplied. As a result, the read data transmitted from the output selection circuit O5L via the differential transistors T9 and TIO is transmitted via the open emitter type output transistor Tll by setting the timing signal φoe to a high level.

As described above, the dynamic RAM of this embodiment has both an ECL input circuit, a TTL input circuit, an ECL output circuit, and a TTL output circuit in response to data input/output signals, address input signals, input control signals, etc. are provided respectively. These input circuits and output circuits are selectively connected to each other by selectively forming predetermined connection wirings displayed as connection switching units SCI to SC3 by the master slice according to the levels of the corresponding input signals and output signals. Considered valid. That is, in this embodiment, dynamic RAMs compatible with the EC'L interface and the TTL interface can be designed and developed at the same time. This allows dynamic RAM
It is possible to shorten the time required for development, reduce the number of development steps, and realize cost reduction.

As shown in the above embodiment, when the present invention is applied to a semiconductor integrated circuit device such as a dynamic RAM,
The following effects can be obtained. That is, (1) A semiconductor integrated circuit device such as a dynamic RAM is provided with a plurality of input circuits and output circuits that are compatible with each of the ECL interface and the TTL interface, and these input circuits and output circuits are connected by master slicing. By selectively enabling the input signal and the output signal, it is possible to simultaneously design and develop a semiconductor integrated circuit device that is compatible with a plurality of input/output interfaces.

(2) According to the above (11), it is possible to shorten the development period of a semiconductor integrated circuit device that is compatible with a plurality of input/output interfaces.

(3) Items (1) and (2) above have the effect of reducing the number of steps required to develop a semiconductor integrated circuit device that can be adapted to a plurality of input/output interfaces, and reducing the cost thereof.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in this embodiment, an ECL input circuit and a TTL input circuit and an ECL
The output circuit and the 1" T L output circuit are selectively enabled by selectively forming connection switching parts SCI to SC3 made of aluminum layers by master slicing. The dynamic RAM may be selectively enabled by selectively disconnecting it according to the level.The dynamic RAM may be one that is compatible with three or more input/output interfaces, for example. , the dynamic RAM is 4
The memory array may have more than one memory array, or may employ an address multiplex method.

Furthermore, the ECL input circuit EIC shown in FIG.

TTL input circuit TIC and ECL output circuit EOC.

Various embodiments may be adopted, including the specific circuit configuration of the TTL output circuit TOC, the block configuration of the dynamic RAM shown in FIG. 2, and combinations of each control signal and address signal.

The above explanation will mainly focus on the dynamic type RA, which is the application field that is the background of the invention made by the present inventor.
Although the case where the present invention is applicable to M is described, the present invention is not limited thereto, and can be applied to other semiconductor storage devices and digital devices, for example. The present invention is widely applicable to semiconductor integrated circuit devices that are required to be compatible with at least a plurality of input/output interfaces.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a semiconductor integrated circuit device such as a Guinamisoku type RAM is provided with a plurality of input circuits and output circuits that can be adapted to each of an ECL interface and a TTL interface, and these input circuits and output circuits are connected to input signals and output circuits by a master slice. By selectively enabling the output signal according to the level of the output signal, it is possible to simultaneously design and develop a semiconductor integrated circuit device that is compatible with a plurality of input/output interfaces. As a result, it is possible to shorten the development period of a semiconductor integrated circuit device that is compatible with a plurality of input/output interfaces, and also to reduce the number of development steps and costs.

[Brief explanation of the drawing]

Figure 1 shows a Guinaminck type RAM to which this invention is applied.
FIG. 2 is a circuit diagram showing an example of the data input/output circuit of FIG.
1 is a block diagram illustrating an embodiment of a 7-inch RAM; FIG. MARYO, MARYI...Memory array, 5APO
, 5API, 5ANO, 5ANI... sense amplifier,
cso, csi...column switch, CAD...column address decoder, RADO, RADI...row address decoder, PCAD...bricolumn address decoder, PRAD...prerow address decoder,
CAB...Column address decoder, RAB...Row address decoder, AMX...Address multiplex injection, RFC...Refresh address counter, M
AO, MAL...main amplifier, Ilo...data input/output circuit, TG...timing generation circuit. EIC...ECL input circuit, TIC...TTL input circuit, EOC...ECL output circuit, TOC...T
T L output circuit, O3L...output selection circuit, BCNl
, BCN2...Bipolar/CMOS inverter circuit, BCGI, BeO2...Bipolar/CMOS Nant gate circuit, NAGI...CMO3/7 gate circuit, N0G1...CMOS NOR gate circuit, N1~
N8...CMOS inverter circuit, DLL, DL2.
...Delay circuit, Q1~Q1o...N channel MO3
FET,,Q21~Q22...P channel MO3F
ET, Tl to T], 9...NPN type bipolar transistor, SCI to SC3... connection switching section.

Claims (1)

Claims: 1. A semiconductor integrated circuit device comprising a plurality of input circuits and/or output circuits that are selectively enabled according to the levels of input signals and/or output signals. 2. The plurality of input circuits include an ECL input circuit and a TTL input circuit provided corresponding to input signals of ECL level and TTL level, and the plurality of output circuits include
It includes an ECL output circuit and a TTL output circuit that are provided corresponding to L level and TTL level output signals, and the ECL input circuit and TTL input circuit and the ECL output circuit and TTL output circuit are connected to each other by a predetermined connection. 2. The semiconductor integrated circuit device according to claim 1, wherein the wiring is selectively made effective by being selectively formed by a master slice. 3. The semiconductor integrated circuit device described above is a dynamic RAM.
Claim 1 or 2 characterized in that
The semiconductor integrated circuit device described in .