JPS59167058A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59167058A
JPS59167058A JP4089783A JP4089783A JPS59167058A JP S59167058 A JPS59167058 A JP S59167058A JP 4089783 A JP4089783 A JP 4089783A JP 4089783 A JP4089783 A JP 4089783A JP S59167058 A JPS59167058 A JP S59167058A
Authority
JP
Japan
Prior art keywords
film
wiring
electrode wiring
titanium silicide
titanium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4089783A
Other languages
Japanese (ja)
Inventor
Yoshimi Shiotani
喜美 塩谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4089783A priority Critical patent/JPS59167058A/en
Publication of JPS59167058A publication Critical patent/JPS59167058A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain an electrode wiring of high reliability by preventing the diffusion of titanium and the oxidation of titanium silicide by a method wherein an aperture is bored by adhering an oxide film on a semiconductor substrate, and, when a titanium silicide electrode wiring contacting an element region is provided thereon, a nitride film is interposed between said wiring and the oxide film. CONSTITUTION:A P type region is diffusion-formed in the N type semiconductor substrate 1, an N type region 2 is provided therein, the aperture is bored by adhering the SiO2 film 6 over the entire surface, and, when the TiSi2 electrode wiring 3 contacting the region 2 is adhered, the following process is taken. That is, the thin Si3N4 film 4 of approx. 1,000Angstrom is interposed without putting the wiring in direct contact with the film 6. Thereafter, the wiring 3 is also covered with a thin Si3N4 film 5, and a PSG film 7 is adhered thereon. Thus, the change of properties of the TiSi2 film 3 is prevented by wrapping said film 3 with the Si3N4 films 4 and 5.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明は半導体装置、特に集積回路(IC)などの半導
体装置に設けられる電極配線の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to the structure of electrode wiring provided in a semiconductor device such as an integrated circuit (IC).

山) 技術の背景 周知のようにICでは表面に多数の素子を接続するため
の電極配線が設けられており、また高密度高集積化され
たLSIでは電極配線が絶縁膜を介して多層に積層され
ている。
Background of the Technology As is well known, ICs have electrode wiring on their surface to connect a large number of elements, and in high-density and highly integrated LSIs, electrode wiring is laminated in multiple layers with insulating films interposed between them. has been done.

従来、かような電極配線はアルミニウムあるいはその合
金が多かったが、柔らかいアルミニウムを多層に形成す
ることが難しく、多層構造では多結晶シリコンが電極配
線として用いられるようになってきた。しかし、多結晶
シリコンは高抵抗で電気伝導度が低いため、それに代わ
る電極配線材料が検討され、その結果高融点金属あるい
は高融点金属シリサイドが注目され使用されるようにな
った。
Conventionally, such electrode wiring has often been made of aluminum or its alloy, but it is difficult to form multiple layers of soft aluminum, so polycrystalline silicon has come to be used as the electrode wiring in multilayer structures. However, since polycrystalline silicon has high resistance and low electrical conductivity, alternative electrode wiring materials have been investigated, and as a result, high melting point metals or high melting point metal silicides have attracted attention and come to be used.

高融点金属とはモリブデン(Mo) 、タングステン(
W)、タンタル(Ta) 、チタン(Ti)などであり
、高融点金属シリサイドはそのシリサイド即ちMoSi
2 、 WSi2 、 TaSi2 、 TiSi2な
どである。
High melting point metals include molybdenum (Mo), tungsten (
W), tantalum (Ta), titanium (Ti), etc., and the high melting point metal silicide is the silicide, that is, MoSi.
2, WSi2, TaSi2, TiSi2, etc.

その内、高融点金属シリサイドは多結晶シリコンに類似
の加工性を有しており、しかも抵抗率が多結晶シリコン
より2桁程度低いために特に重用されつつある。
Among them, high-melting point metal silicide has processability similar to that of polycrystalline silicon, and has a resistivity that is about two orders of magnitude lower than that of polycrystalline silicon, so it is becoming particularly important.

(C1従来技術と問題点 このような高融点金属シリサイドにおいてモリブデンシ
リサイド(MoSi2 )が最も良く利用されているが
、モリブデンシリサイドをプラズマ気相成長法で被着形
成すると安定した膜質のものが得られない問題がある。
(C1 Prior art and problems) Molybdenum silicide (MoSi2) is most commonly used as a high melting point metal silicide, but when molybdenum silicide is deposited by plasma vapor deposition, a stable film quality cannot be obtained. There is no problem.

それはソース(気相源)の五塩化モリブデン(MoC1
5)が常温で固体であり、容器を一定温度(約100℃
)に加熱して送入管も絶えず一定に保温しなければなら
ない難問題に原因があるものと考えられる。
It is the molybdenum pentachloride (MoC1) source (gas phase source).
5) is solid at room temperature, and the container is kept at a constant temperature (approximately 100℃).
This is thought to be due to the difficult problem of having to keep the inlet pipe at a constant temperature.

また、プラズマ気相成長法は他の被膜形成法に比べて最
もステップカバレージが良く、凹凸の多い表面に被着す
る電極配線の形成には最も適した被着方法である。
Furthermore, the plasma vapor deposition method has the best step coverage compared to other film forming methods, and is the most suitable deposition method for forming electrode wiring on a surface with many irregularities.

従って、ソースが常温で液体の材料からなる高融点金属
シリサイドをプラズマ気相成長法で被着することが望ま
れる。かような高融点金属シリサイドはチタンシリサイ
ド(TiSi2)で、四塩化チタン(TiC14)が常
温で液状である。しかも、チタンシリサイドは多数のシ
リサイド材料のうち、最も電気伝導度が良い。
Therefore, it is desirable for the source to deposit high-melting point metal silicide made of a material that is liquid at room temperature by plasma vapor deposition. Such high melting point metal silicide is titanium silicide (TiSi2), and titanium tetrachloride (TiC14) is liquid at room temperature. Furthermore, titanium silicide has the best electrical conductivity among many silicide materials.

しかし一方、チタンシリサイドは化学的に活性で、酸化
しやすい等の欠点がある。
However, on the other hand, titanium silicide has drawbacks such as being chemically active and easily oxidized.

+d)  発明の目的 本発明はこのような問題に解決を与えて、チタンシリサ
イドを電極配線とした構造の半導体装置を提案するもの
である。
+d) Purpose of the Invention The present invention provides a solution to such problems and proposes a semiconductor device having a structure in which titanium silicide is used as electrode wiring.

(e)  発明の構成 その目的は、チタンシリサイド層と酸化物層との間に窒
化シリコン膜が介在してなる半導体装置によって達成す
ることができる。
(e) Structure of the Invention The object can be achieved by a semiconductor device in which a silicon nitride film is interposed between a titanium silicide layer and an oxide layer.

(fl  発明の実施例 以下2図面を参照して実施例によって詳細に説明する。(fl Embodiments of the invention Examples will be described in detail below with reference to two drawings.

第1図は本発明にかかる一実施例の断面図を示し、半導
体基板1のN型領域2からチタンシリサイド電極配線3
を導出しており、このチタンシリサイド電極配線の下層
と上層とを膜厚1000人の窒化シリコン(St、N4
)膜4.5で被覆している。6は二酸化シリコン(Si
O2)ML7は燐シリケートガラス(P S G)膜で
ある。
FIG. 1 shows a cross-sectional view of one embodiment of the present invention, and shows a titanium silicide electrode wiring 3 from an N-type region 2 of a semiconductor substrate 1.
The lower and upper layers of this titanium silicide electrode wiring are made of silicon nitride (St, N4) with a thickness of 1000.
) coated with membrane 4.5. 6 is silicon dioxide (Si
O2) ML7 is a phosphorus silicate glass (PSG) membrane.

このような構造にすると、チタンシリサイドが5i02
膜やpsc膜のような酸化膜と直接接触することがない
から、チタンが拡散したりチタンシリサイドが酸化した
りすることが防止され安定である。その形成方法は、下
層の窒化シリコン膜4をプラズマ気相成長法で被着した
後にチタンシリサイド3をプラズマ気相成長法で被着し
てパターンニングする。次いで、上層の窒化シリコン膜
5をプラズマ気相成長法で被着し、更に不必要な部分に
被着した窒化シリコン膜はフォトプロセスによって除去
する。このようにすれば、完全にチタンシリサイドを窒
化シリコン膜で被覆することができる。
With this structure, titanium silicide becomes 5i02
Since there is no direct contact with an oxide film such as a film or a PSC film, diffusion of titanium and oxidation of titanium silicide are prevented and stability is maintained. Its formation method is to deposit the lower silicon nitride film 4 by plasma vapor phase epitaxy, then deposit titanium silicide 3 by plasma vapor phase epitaxy and pattern it. Next, an upper silicon nitride film 5 is deposited by plasma vapor deposition, and the silicon nitride film deposited on unnecessary portions is removed by a photo process. In this way, titanium silicide can be completely covered with the silicon nitride film.

次ぎに、第2図は本発明にかかる他の実施例の断面図で
ある。本例は半導体基板11上にゲート絶縁膜12を介
して多結晶シリコン膜(ゲート電極)13が設けられ、
多結晶シリコン膜は導電性が悪いため多結晶シリコン膜
13に接着してチタンシリサイド14を形成した構造で
、電極配線は多結晶シリコン13とチタンシリサイド1
4とから構成されている。この場合は、上層のみ窒化シ
リコン膜15で被覆すれば十分にチタンシリサイドの変
質が防がれる。尚、16は二酸化シリコン膜、17は燐
シリケートガラス膜である。
Next, FIG. 2 is a sectional view of another embodiment according to the present invention. In this example, a polycrystalline silicon film (gate electrode) 13 is provided on a semiconductor substrate 11 via a gate insulating film 12,
Since the polycrystalline silicon film has poor conductivity, it has a structure in which titanium silicide 14 is bonded to the polycrystalline silicon film 13, and the electrode wiring is made of polycrystalline silicon 13 and titanium silicide 1.
It is composed of 4. In this case, if only the upper layer is covered with the silicon nitride film 15, deterioration of the titanium silicide can be sufficiently prevented. Note that 16 is a silicon dioxide film and 17 is a phosphorus silicate glass film.

(梢 発明の効果 以上の説明から明らかなように、本発明は高融点金属シ
リサイドの中で最も電気伝導度の良いチタンシリサイド
を安定して電極配線にする構造である。従って、本発明
によればIC,、LSIなどの半導体装置を高性能化す
ることができる。
(Kozue) Effects of the Invention As is clear from the above explanation, the present invention has a structure in which titanium silicide, which has the highest electrical conductivity among refractory metal silicides, is stably used as electrode wiring. For example, it is possible to improve the performance of semiconductor devices such as ICs and LSIs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は何れも本発明にかかる実施例の断
面構造図である。 図中、1.11は半導体基板、2はN型領域。 3.14はチタンシリサイド、4,5.15は窒化シリ
コン1g、6.16は二酸化シリコン膜、7゜17は燐
シリケートガラス膜、12はゲート絶縁膜1,13は多
結晶シリコン膜を示している。
Both FIG. 1 and FIG. 2 are cross-sectional structural views of an embodiment according to the present invention. In the figure, 1.11 is a semiconductor substrate, and 2 is an N-type region. 3.14 is titanium silicide, 4, 5.15 is 1 g of silicon nitride, 6.16 is a silicon dioxide film, 7°17 is a phosphorus silicate glass film, 12 is a gate insulating film 1, 13 is a polycrystalline silicon film. There is.

Claims (1)

【特許請求の範囲】[Claims] チタンシリサイド層と酸化物層との間に窒化シリコン膜
が介在してなることを特徴とする半導体装置。
A semiconductor device characterized in that a silicon nitride film is interposed between a titanium silicide layer and an oxide layer.
JP4089783A 1983-03-11 1983-03-11 Semiconductor device Pending JPS59167058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4089783A JPS59167058A (en) 1983-03-11 1983-03-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4089783A JPS59167058A (en) 1983-03-11 1983-03-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59167058A true JPS59167058A (en) 1984-09-20

Family

ID=12593298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4089783A Pending JPS59167058A (en) 1983-03-11 1983-03-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59167058A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6350043A (en) * 1986-08-19 1988-03-02 Mitsubishi Electric Corp Inter-layer insulating film for semiconductor device
JPS6444044A (en) * 1987-08-12 1989-02-16 Fujitsu Ltd Manufacture of semiconductor device
US4807015A (en) * 1984-12-24 1989-02-21 Hitachi, Ltd. Semiconductor device having electrodes and or interconnections of refractory metal film containing silicon oxide
JP2013084829A (en) * 2011-10-12 2013-05-09 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5487175A (en) * 1977-12-23 1979-07-11 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5487175A (en) * 1977-12-23 1979-07-11 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4807015A (en) * 1984-12-24 1989-02-21 Hitachi, Ltd. Semiconductor device having electrodes and or interconnections of refractory metal film containing silicon oxide
JPS6350043A (en) * 1986-08-19 1988-03-02 Mitsubishi Electric Corp Inter-layer insulating film for semiconductor device
JPS6444044A (en) * 1987-08-12 1989-02-16 Fujitsu Ltd Manufacture of semiconductor device
JP2013084829A (en) * 2011-10-12 2013-05-09 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same

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