JPH02140957A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a coated glass film from cracking, and to improve yield and reliability by etching back a silicon oxide film vapor reacted with organic silane as an interlayer insulating film between metals, and then laminating the coated glass layer. CONSTITUTION:A field oxide film 12 is formed on a silicon substrate 11, and first metal interconnection 13 opened with a contact hole for leading an electrode is formed. A first silicon oxide film 14 is grown in plasma with TEOS [Si(OC2H5)4] and O2 as reaction gases as an interlayer insulating film by a parallel flat plate vapor growing apparatus. Subsequently, the TEOS is vapor reacted with ozone, a second silicon oxide film 15 is laminated, dry etched in a predetermined thickness, then coated with a coated glass film 16, annealed, a through hole is then formed, Al alloy is sputtered, and photoetched to form a second metal interconnection 17. Thus, it prevents the film 16 from cracking, and yield and reliability are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure for multifunction and integration.

[Conventional techniques (E11) Conventionally, the manufacturing method of semiconductor devices with multilayer wiring structure is 1
For example, as shown in FIG. 2, after opening a contact hole to take out an electrode from the element through the field insulating film 22 on the silicon substrate 21 in which semiconductor elements such as transistors and resistors are formed, After spuckling the alloy and spacing it into a desired shape by etching to form the first metal wiring 23, an interlayer insulating film is first grown at 1° EO3 at 370 to 400°C using a parallel plate vapor phase growth apparatus. [S i (OC2IIs) 4) and oxygen (02) are used as reaction gases, the first silicon oxide film 24 is grown to a thickness of about 0.6 μm by plasma at a pressure of 5 torr or less, and the second silicon oxide film 24 is grown by thermally reacting TE01 and ozone. A silicon oxide film 25 is laminated.

This interlayer insulating film is made of Sin< and 02 or Ne at low temperature.
Unlike a silicon oxide film grown in a vapor phase using O gas under reduced pressure, there is no cusping and it is easy to adhere to.

Next, for flattening, a coated glass film 26 is applied and annealed, and a through hole is formed by photo-etching.
A1 alloy is sputtered and then photoetched to form the second metal wiring 27, and then the passivation crotch is J, FI lff1.

[Problem to be solved by the invention]

However, with conventional technology, as design rules approach sub-micron scale with the miniaturization of LSIs, the spacing of metal wiring, which requires dimensional accuracy, becomes dry etching, resulting in a steeper cross-sectional shape and an aspect ratio of approximately 0. .7 or more, so even if the coverage of the first layer of insulation is good, a groove corresponding to the thickness of the first metal wiring is formed in the space of the first metal wiring, so there is only a pool of coated glass there. Cracks and peeling occur where the thickness is thicker than 0.5 μm, resulting in contamination traps, particles, and breakage and short circuits in the second metal wiring, causing yield and reliability problems. . Furthermore, in the future, (I
! ! Due to demands for metal lamination and reflow planarization using bias sputtering, the first metal interconnect 23 tends to become thicker, and the aspect ratio becomes increasingly strict, making it important to improve coverage and planarize the first interlayer insulating film. It's coming.

However, the present invention is intended to solve such problems, and aims to flatten a semiconductor device having multilayer wiring, eliminate cracks in the coated glass film, and improve yield and reliability. It is.

[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention is to react organic silane with a gas containing oxygen or ozone after forming at least a first metal wiring in a semiconductor device having a multilayer wiring structure. a step of stacking a vapor-grown oxide film, a step of dry-etching the vapor-grown oxide film to a predetermined thickness, and then corrugating and annealing the coated glass film; and a step of forming a through hole to form a second metal layer. The method is characterized by comprising a step of forming wiring.

[Example] An example of the present invention will be described in detail based on FIG. A silicon substrate 1 in which semiconductor components such as transistors and resistors are fabricated when applied to a Stgegoo CMOS-IC manufactured by AI2JiItM with a submicron rule.
Field oxidation by selective thermal oxidation or vapor phase growth on 11
1X12 was formed, a contact hole was opened for mti extraction, and A1 alloy containing about 0.5% CLl was spackled to a thickness of about 0.7 um, and photolithographic f
Dry etched with &c+t gas, minimum dimension is 0.8
The first metal gap 41+ whose side surface is approximately 1.2 Bm straight! First, as a 0-order interlayer paper I1 film subjected to 13
TEOS [S i (OC-MS) 4] and 0
．． The first silicon oxide film 14 was grown by about 0.6 .mu.n1 in a plasma of about 2 torr using the reaction gas. TEOS and ozone are continuously reacted in the gas phase, and a 0.4 um second
The silicon oxide film 15 of
．． After anisotropic etching of about 4 μm, coated glass 1
After applying l16 and annealing at 400°C, through holes were formed and A1 alloy was spackled to a thickness of about 1.0 μm.

This was photoetched to form the second metal arrangement 1i! After that, a passivation film was laminated and a pad portion for taking out an external electrode was opened.

The semiconductor device formed in this way has a $1
The flatness of the interlayer insulating film in the space 113 is improved,
Therefore, the thickness of the liquid pool of coated glass that enters here is 0°4μ.
m or less, and no cracks were generated. On the other hand, we also produced a prototype in which the coated glass film 16, which has a lot of contamination, was etched back, a vapor-grown silicon oxide film was deposited again, and through-holes were formed to form the second metal wiring 17, but the flatness did not improve. , we were able to further improve reliability. In addition to CHFa gas, etchback can also be performed using CF,
, C@Fs can be substituted, the etching may be isotropic, and etchback using Ar spuck etching can also be used.

The present invention is applicable not only to interlayer insulating films of MOSICs but also to bibolar and OMO3 ICs, and ICs combining these. Furthermore, the metal wiring is not limited to A1 and A1 alloys, but may also be other metals, silicides, or semiconductor materials.
It is also possible to use laminated films of high-melting point metals such as Ti, W, Go, and Mo, or their nitrides, silicides, and alloys for the purpose of forming a concrete barrier.

〔Effect of the invention〕

As described above, according to the present invention, a silicon oxide film subjected to a vapor phase reaction of organic silane is edge-backed as a film between metals such as MO5LSI, and then a coated glass film is subjected to f(IF!j). By this, cracks in the insulation H2,
This eliminates peeling, improves yield and reliability, and facilitates multi-layering of fine metal wiring, contributing to the supply of more integrated and multi-functional semiconductor devices.

Figure 2 shows It is a diagram.

Schematic cross section of a conventional semiconductor device 11° 12° 13° l 4. 15° 16° 1? .

21・ 22・ 23・ 24・ 25・ 26・ 27・ 1 silicon base field oxide film first metal wiring First silicon oxide film Second silicon oxide film coated glass film second metal wiring Below Up

Claims (1)

[Claims] In a semiconductor device having a multilayer wiring structure, after forming at least a first metal wiring, a step of laminating a vapor-grown oxide film made by reacting an organic silane with a gas containing oxygen or ozone; A method for manufacturing a semiconductor device, comprising the steps of: dry etching to a predetermined thickness, then applying a coated glass film and annealing; and forming a through hole to form a second metal wiring.