JPH04186730A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04186730A JPH04186730A JP31533790A JP31533790A JPH04186730A JP H04186730 A JPH04186730 A JP H04186730A JP 31533790 A JP31533790 A JP 31533790A JP 31533790 A JP31533790 A JP 31533790A JP H04186730 A JPH04186730 A JP H04186730A
- Authority
- JP
- Japan
- Prior art keywords
- film
- tungsten
- melting point
- point metal
- high melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000002844 melting Methods 0.000 claims abstract description 24
- 230000008018 melting Effects 0.000 claims abstract description 23
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 32
- 229910052721 tungsten Inorganic materials 0.000 abstract description 32
- 239000010937 tungsten Substances 0.000 abstract description 32
- 238000004544 sputter deposition Methods 0.000 abstract description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 6
- 239000010936 titanium Substances 0.000 abstract description 6
- 229910052719 titanium Inorganic materials 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 4
- 238000001459 lithography Methods 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 3
- 239000007789 gas Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 50
- 239000011229 interlayer Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に、高融点金
属配線の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a high melting point metal wiring.
半導体装置の微細化・高密度化が進むにつれ、配線は益
々微細化され、エレクトロマイグレーションやストレス
マイグレーションに対スる耐性が強い配線材料が求めら
れている。このような要求にこたえるため、近年通常側
われているアルミニウムに）わり高融点金属を配線に使
用することが検討されている。（Ｐｒｏｃ、６ｔｈ Ｉ
ｎｔ、ＶＭＩＣｐ４０゜１９８９やＰｒｏｃ、６ｔｈ
Ｉｎｔ、ＶＭＩＣｐ１９，１９８９など）これら高融点
金属膜は、通常化学気相成長法もしくはマグネトロンス
パッタリング法により形成されるが、従来は上記２方法
のうちどちらか一方の方法で形成されていた。BACKGROUND ART As semiconductor devices become smaller and more dense, interconnections are becoming increasingly finer, and there is a need for interconnection materials that are highly resistant to electromigration and stress migration. In order to meet these demands, in recent years the use of high melting point metals (instead of aluminum, which is commonly used) for wiring has been considered. (Proc, 6th I
nt, VMICp40゜1989 and Proc, 6th
Int, VMIC p19, 1989, etc.) These high melting point metal films are usually formed by chemical vapor deposition or magnetron sputtering, but conventionally they have been formed by one of the above two methods.
化学気相成長法で高融点金属膜を形成すると表面の凹凸
が大きく、配線として使用する場合に必要な微細加工が
困難という問題を有している。When a high melting point metal film is formed by chemical vapor deposition, the surface has large irregularities, making it difficult to perform microfabrication necessary for use as wiring.
ｉた、マグネトロンスパッタリング法で高融点金属膜を
形成すると、化学気相成長法で形成した場合に比べ高融
点金属の比抵抗が大きくなるという欠点を有している。Additionally, when a high melting point metal film is formed by magnetron sputtering, it has the disadvantage that the specific resistance of the high melting point metal becomes larger than when it is formed by chemical vapor deposition.
本発明の目的は上記欠点を排除し、比抵抗が小さくしか
も表面の凹凸が比較的小さい高融点金属膜の形成方法を
提供することである。An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a method for forming a high melting point metal film having a low specific resistance and a relatively small surface unevenness.
本発明は、半導体装置の配線を形成する工程において、
化学気相成長法（ＣＶＤ法）により高融点金属膜を形成
する工程と、引き続きマグネトロンスパッタリング法（
スパッタ法）により同種の高融点金属膜を形成する工程
とを有している。In the process of forming wiring of a semiconductor device, the present invention includes:
A process of forming a high melting point metal film by chemical vapor deposition (CVD) followed by magnetron sputtering (
The method includes a step of forming a high melting point metal film of the same type by a sputtering method.
本発明の製造方法によれば、ＣＶＤ法により形成する高
融点金属膜の厚さを薄くすることができるので表面の凹
凸を小さくすることができる。また引き続きスパッタ法
により高融点金属膜を形成すると、下地の結晶構造を反
映した高融点金属膜が形成されるのでＣＶＤ法により形
成された高融点金属膜の比抵抗に近い低い比抵抗値をも
つ高融点金属膜が形成される。According to the manufacturing method of the present invention, the thickness of the high-melting point metal film formed by the CVD method can be reduced, so that surface irregularities can be reduced. Furthermore, when a high melting point metal film is subsequently formed by sputtering, a high melting point metal film is formed that reflects the crystal structure of the underlying layer, so it has a low resistivity value close to that of a high melting point metal film formed by CVD. A high melting point metal film is formed.
したがって、比抵抗でかつ微細加工の比較的容易な高融
点金属膜を形成することができる。Therefore, it is possible to form a high melting point metal film that has a high resistivity and is relatively easy to microfabricate.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｃ）は本発明の第１の実施例な説明す
るための工程順断面ズである。FIGS. 1(a) to 1(c) are cross-sectional views of a first embodiment of the present invention in the order of steps for explaining it.
（ａ）表面に高濃度不純物領域２を有するシリコン基板
１上に層間絶縁膜３を約０．５形成した後、リングラフ
イー工程を経てピアホール４を形成する。素子分離領域
や素子の形成は省略されている。(a) After forming about 0.5 of an interlayer insulating film 3 on a silicon substrate 1 having a high-concentration impurity region 2 on its surface, a pier hole 4 is formed through a ring graphie process. Formation of element isolation regions and elements is omitted.
（ｂ） スパッタ法によりチタン膜５を約０．１μｍ
、窒化チタン膜を約０．１μｍ形成する。(b) The titanium film 5 is approximately 0.1 μm thick by sputtering.
, a titanium nitride film with a thickness of about 0.1 μm is formed.
（ｃ）六弗化タングステンガスと水素ガスを用いてＣＶ
Ｄ法によりタングステン膜７を約０１μｍ形成する。(c) CV using tungsten hexafluoride gas and hydrogen gas
A tungsten film 7 with a thickness of about 0.1 μm is formed by method D.
（ｄ） スパッタ法によりタングステン膜８を約０．
５μｍ形成する。(d) Sputtering the tungsten film 8 to about 0.00 mm.
Form 5 μm.
（ｅ） リソグラフィー工程を経てバターニングを行
なう。(e) Buttering is performed through a lithography process.
このようにして形成されたタングステン配線は、高濃度
不純物領域２とチタン膜５が接しているのでピアホール
の接続抵抗が小さく、チタン膜５とタングステン膜７の
間に存在する窒化チタン膜６が高濃度不純物領域２の表
面にシリコンがタングステン膜７およびタングステン膜
８の中へ拡散するのを防いでいるので安定したピアホー
ル構造となっている。また、ＣＶＤタングステン膜７の
膜厚が約０．１μｍと薄いので表面の凹凸は小さく、し
かもＣＶＤタングステン膜７上にスパッタタングステン
膜８を形成しているのでスパッタタングステン膜８の比
抵抗は小さくなっている。In the tungsten wiring formed in this way, the connection resistance of the peer hole is low because the high concentration impurity region 2 and the titanium film 5 are in contact with each other, and the titanium nitride film 6 existing between the titanium film 5 and the tungsten film 7 has a high Silicon on the surface of the concentrated impurity region 2 is prevented from diffusing into the tungsten film 7 and the tungsten film 8, resulting in a stable peer hole structure. Furthermore, since the CVD tungsten film 7 has a thin film thickness of about 0.1 μm, the surface unevenness is small, and since the sputtered tungsten film 8 is formed on the CVD tungsten film 7, the specific resistance of the sputtered tungsten film 8 is small. ing.
したがって低抵抗でありかつ微細加工性に優れた配線構
造になっている。Therefore, the wiring structure has low resistance and excellent microfabriability.
第２図（ａ）〜（ｅ）は本発明の第２の実施例を説明す
るための工程順断面図である。本実施例は第１の実施例
に引き続いて第２層タングステン配線を形成したもので
ある。FIGS. 2(a) to 2(e) are step-by-step sectional views for explaining a second embodiment of the present invention. In this example, a second layer of tungsten wiring was formed following the first example.
（、） 第１の実施例で示したように第１層タングス
テン配線を形成する。(,) A first layer tungsten wiring is formed as shown in the first embodiment.
（ｂ） 層間絶縁膜９を約０．５μｍ形成した後、リ
ソグラフィー工程を経てピアホール１０を形成する。(b) After forming an interlayer insulating film 9 of about 0.5 μm, a pier hole 10 is formed through a lithography process.
（ｃ） 六弗化タングステンガスと水素ガスを用いて
ＣＶＤ法によりタングステン膜１１を約０．１μｍ形成
する。(c) A tungsten film 11 having a thickness of approximately 0.1 μm is formed by CVD using tungsten hexafluoride gas and hydrogen gas.
（ｄ）スパッタ法によりタングステンｆｆ１１２ヲ約０
．５μｍ形成する。(d) Approximately 0 tungsten ff112 by sputtering method
．． Form 5 μm.
（ｅ） リソグラフィー工程を経てパターニングを行
なう。(e) Patterning is performed through a lithography process.
このように形成された第２層タングステン配線は、ＣＶ
Ｄタングステン膜１１の膜厚が約０．１μｍと薄いので
表面の凹凸が小さい。しかも、ＣＶＤタングステン膜１
１上にスパッタタングステン膜１２を形成しているので
スパッタタングステン膜１２の比抵抗は小さくなってい
る。したがって、低抵抗でありかつ微細加工性に優れた
配線構造になっている。The second layer tungsten wiring formed in this way has a CV
Since the thickness of the D tungsten film 11 is as thin as approximately 0.1 μm, surface irregularities are small. Moreover, CVD tungsten film 1
Since the sputtered tungsten film 12 is formed on the sputtered tungsten film 1, the specific resistance of the sputtered tungsten film 12 is small. Therefore, the wiring structure has low resistance and excellent microfabriability.
以上説明したように本発明は、ＣＶＤ法により高融点金
属膜を形成し引き続いてスパッタ法により同種の高融点
金属膜を形成する方法により配線の金属膜を形成してい
るので、配線の表面の凹凸が小さく微細加工性に優れた
配線を提供することができる。しかも、スパッタタング
ステン膜の比抵抗を小さくすることができ、低抵抗の配
線を提供することができる。As explained above, in the present invention, the metal film of the wiring is formed by the method of forming a high melting point metal film by CVD method and then forming the same kind of high melting point metal film by sputtering method. It is possible to provide wiring with small irregularities and excellent microfabricability. Moreover, the specific resistance of the sputtered tungsten film can be reduced, and low-resistance wiring can be provided.
したがって本発明によれば、エレクトロマイグレーショ
ン耐性やストレスマイグレーション耐性に優れ、低抵抗
であり、かつ、微細加工の容易な配線を提供することが
できるので半導体装置の微細化および高密度化を進める
効果を有する。Therefore, according to the present invention, it is possible to provide wiring that has excellent electromigration resistance and stress migration resistance, has low resistance, and is easy to microfabricate, so that it is possible to provide wiring that is easy to microfabricate and is effective in promoting miniaturization and high density of semiconductor devices. have
尚、実施例においては高融点金属膜としてタングステン
膜を用いているが、モリブデン膜等の他の高融点金属膜
を用いても同様の効果を有することは明らかである。In the embodiment, a tungsten film is used as the high melting point metal film, but it is clear that the same effect can be obtained even if other high melting point metal films such as a molybdenum film are used.
第１図（ａ）〜（ｅ）は本発明の第１の実施例を説明す
るための工程順断面図であり、第２図（ａ）〜（ｅ）は
本発明の第２の実施例を説明するための工程順断面図で
ある。
１・・・・・・シリコン基板、２・・・・・・高濃度不
純物領域、３・・・・・・層間絶縁膜、４・・・・・・
ピアホール、５・・・・・・チタン膜、６・・・・・・
窒化チタン膜、７・・・・・ＣＶＤタングステン膜、８
・・・・・・スパッタタングステン膜、９・・・・・・
層間絶縁膜、１０・・・・・・ピアホール、１１・・・
・・ＣＶＤタングステン膜、１２・・・・・・スパッタ
タングステン膜。
代理人 弁理士 内 原 晋
第１図
第２ 図FIGS. 1(a) to (e) are step-by-step sectional views for explaining the first embodiment of the present invention, and FIGS. 2(a) to (e) are sectional views of the second embodiment of the present invention. FIG. 3 is a step-by-step sectional view for explaining the process. 1...Silicon substrate, 2...High concentration impurity region, 3...Interlayer insulating film, 4...
Pier hole, 5...Titanium film, 6...
Titanium nitride film, 7...CVD tungsten film, 8
...Sputtered tungsten film, 9...
Interlayer insulating film, 10... Pier hole, 11...
...CVD tungsten film, 12...sputtered tungsten film. Agent: Susumu Uchihara, patent attorney Figure 1 Figure 2
Claims (1)
長法により高融点金属膜を形成する工程と、引き続きマ
グネトロンスパッタリング法により前記高融点金属膜と
同種の高融点金属膜を形成する工程とを有することを特
徴とする半導体装置の製造方法。The process of forming wiring for a semiconductor device includes the steps of forming a high melting point metal film by chemical vapor deposition, and subsequently forming a high melting point metal film of the same type as the high melting point metal film by magnetron sputtering. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31533790A JPH04186730A (en) | 1990-11-20 | 1990-11-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31533790A JPH04186730A (en) | 1990-11-20 | 1990-11-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04186730A true JPH04186730A (en) | 1992-07-03 |
Family
ID=18064198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31533790A Pending JPH04186730A (en) | 1990-11-20 | 1990-11-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04186730A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010077743A (en) * | 2000-02-08 | 2001-08-20 | 박종섭 | Bit line and manufacturing method thereof |
-
1990
- 1990-11-20 JP JP31533790A patent/JPH04186730A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010077743A (en) * | 2000-02-08 | 2001-08-20 | 박종섭 | Bit line and manufacturing method thereof |
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