JPS59165524A - ＧａＡｓ論理集積回路 - Google Patents

ＧａＡｓ論理集積回路

Info

Publication number
JPS59165524A
JPS59165524A JP58037499A JP3749983A JPS59165524A JP S59165524 A JPS59165524 A JP S59165524A JP 58037499 A JP58037499 A JP 58037499A JP 3749983 A JP3749983 A JP 3749983A JP S59165524 A JPS59165524 A JP S59165524A
Authority
JP
Japan
Prior art keywords
dfet
gaas
fet
circuit
normally
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58037499A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0347776B2 (enrdf_load_stackoverflow
Inventor
Yasuo Igawa
井川　康夫
Akimichi Hojo
北條　顕道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP58037499A priority Critical patent/JPS59165524A/ja
Publication of JPS59165524A publication Critical patent/JPS59165524A/ja
Publication of JPH0347776B2 publication Critical patent/JPH0347776B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
JP58037499A 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路 Granted JPS59165524A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58037499A JPS59165524A (ja) 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58037499A JPS59165524A (ja) 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路

Publications (2)

Publication Number Publication Date
JPS59165524A true JPS59165524A (ja) 1984-09-18
JPH0347776B2 JPH0347776B2 (enrdf_load_stackoverflow) 1991-07-22

Family

ID=12499212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58037499A Granted JPS59165524A (ja) 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路

Country Status (1)

Country Link
JP (1) JPS59165524A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0347776B2 (enrdf_load_stackoverflow) 1991-07-22

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