JPS59159034U

JPS59159034U - Binarization device

Info

Publication number: JPS59159034U
Application number: JP5297883U
Authority: JP
Inventors: 勇二濱崎; 一狭間; 勇田中
Original assignee: 株式会社島津製作所
Priority date: 1983-04-09
Filing date: 1983-04-09
Publication date: 1984-10-25

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来技術を説明するための原理図、第２図は従
来装置の構成を略示したブロック図、第３図はこの考案
の一実施例の構成を略示したブロック図、第４図は第３
図に示した実施例５客部の動作波形図である。１・・・・・・増幅回路、２・・・・・・マルチプレク
サ、３・・・・・・初期設定器、４・・・・・・デコー
ダ、５．１０・・・・・・遅延回路、６・・・・・・減
衰回路、７・・・・・・バイアス回路、８・・・・・・
比較回路、９・・・・・・サンプルホールド、１１・・
・・・・差動増幅回路、１２・・・・・・Ａ／Ｄ変換回
路、Ｒ１−Ｒ２・・・・・・抵抗器。補正　昭５８．　８．　１考案の名称を次のように補正する。 ■二値化装置実用新案登録請求の範囲、図面の簡単な説明を次のよう
に補正する。Ｏ実用新案登録請求の範囲原信号を遅延減衰させるとともにバイアス電圧を与えて
得られたしきい値信号と、増幅回路を介して取り出した
原信号とを比較することにより二値化信号を得る装置で
あって、前記増幅回路の増幅率は、その出力信号としき
い値信号との差動信号”に基づき可変されるものである
ことを特徴とする二値化装置。図面の簡単な説明 −第１図は従来技術を説明するための原理図、第２図ｉ
よ従来装置の構成を略示したブロック図、第３図はこの
考案の一実施例の構成を略示したシロツク図、第４図は
第３図に示した実施例の各部の動作波形図である。１・・・・・・増幅回路、２・・・・・・マルチプレク
サ、３・・・・・・初期設定器、４・・・・・・デコー
ダ、５．１０・・・・・・遅延回路、６・・・・・・減
衰回路、７・・・・・・ノくイアス回路、８・・・・・
・比較回路、９・・・・・・サンプルホールド・・・・
・・差動増幅回路、１２・・・・・・Ａ／Ｄ変換回路、
Ｒ１−Ｒ２・・・・・・抵抗器。Fig. 1 is a principle diagram for explaining the prior art, Fig. 2 is a block diagram schematically showing the structure of a conventional device, Fig. 3 is a block diagram schematically showing the structure of an embodiment of this invention, and Fig. 4 The figure is the third
FIG. 7 is an operational waveform diagram of the customer section of the fifth embodiment shown in the figure. 1...Amplifier circuit, 2...Multiplexer, 3...Initial setter, 4...Decoder, 5.10...Delay circuit , 6... Attenuation circuit, 7... Bias circuit, 8...
Comparison circuit, 9...Sample hold, 11...
... Differential amplifier circuit, 12 ... A/D conversion circuit, R1-R2 ... Resistor. Amended 1984. 8. 1. The name of the invention shall be amended as follows. ■ Binarization device utility model registration The scope of the claims and the brief description of the drawings are amended as follows. O Utility Model Registration Claims Device for obtaining a binary signal by comparing a threshold signal obtained by delaying and attenuating the original signal and applying a bias voltage to the original signal extracted through an amplifier circuit. The binarization device is characterized in that the amplification factor of the amplification circuit is varied based on a differential signal between its output signal and a threshold signal. Figure 1 is a principle diagram for explaining the conventional technology, Figure 2 i
3 is a block diagram schematically showing the configuration of a conventional device, FIG. 3 is a block diagram schematically showing the configuration of an embodiment of this invention, and FIG. 4 is an operating waveform diagram of each part of the embodiment shown in FIG. 3. be. 1...Amplifier circuit, 2...Multiplexer, 3...Initial setter, 4...Decoder, 5.10...Delay circuit , 6... Attenuation circuit, 7... Nokuiasu circuit, 8...
・Comparison circuit, 9...Sample hold...
...Differential amplifier circuit, 12...A/D conversion circuit,
R1-R2...Resistor.

Claims

[Scope of utility model registration request]

A device for obtaining a binarized signal by comparing a threshold signal obtained by delaying and attenuating an original signal and applying a via filter voltage with an original signal taken out via an amplifier circuit, the device comprising: A binarization device characterized in that the amplification factor of the circuit is varied based on a differential signal between its output signal and a threshold signal.