JPS60104954U - data acquisition circuit - Google Patents
data acquisition circuitInfo
- Publication number
- JPS60104954U JPS60104954U JP19701183U JP19701183U JPS60104954U JP S60104954 U JPS60104954 U JP S60104954U JP 19701183 U JP19701183 U JP 19701183U JP 19701183 U JP19701183 U JP 19701183U JP S60104954 U JPS60104954 U JP S60104954U
- Authority
- JP
- Japan
- Prior art keywords
- output
- analog
- data acquisition
- acquisition circuit
- multiplexer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のデータ収集回路図、第２図は本考案の一
実施例を示す回路図である。
１□、１゜、１ｎ・・・アナログ信号源、２ｏ、２ ．
１．２□、２ｎ・・・フィルタ、３・・・マルチプレク
サ、４・・・バッファアンプ、５・・・アナログ−ディ
ジタル変換器。FIG. 1 is a conventional data acquisition circuit diagram, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1□, 1°, 1n...analog signal source, 2o, 2.
1.2□, 2n... Filter, 3... Multiplexer, 4... Buffer amplifier, 5... Analog-digital converter.
Claims (1)
して各アナログ入力信号を時分割的に直列のアナログ信
号列にするマルチプレクサと、このマルチプレクサの出
力からノイズ成分を除去する１つのフィルタと、このフ
ィルタの出力を高入力インピーダンスで受は適当に増幅
する低出力インピーダンスのバッファアンプと、このア
ンプの出力をディジタル信号に変換するアナログ−ディ
ジタル変換器とを備えたことを特徴とするデータ収集回
路。A multiplexer that receives analog output signals from multiple analog signal sources and converts each analog input signal into a serial analog signal train in a time-divisional manner; a filter that removes noise components from the output of the multiplexer; 1. A data acquisition circuit comprising: a low output impedance buffer amplifier that receives and appropriately amplifies an output with a high input impedance; and an analog-to-digital converter that converts the output of this amplifier into a digital signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19701183U JPS60104954U (en) | 1983-12-21 | 1983-12-21 | data acquisition circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19701183U JPS60104954U (en) | 1983-12-21 | 1983-12-21 | data acquisition circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60104954U true JPS60104954U (en) | 1985-07-17 |
Family
ID=30754978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19701183U Pending JPS60104954U (en) | 1983-12-21 | 1983-12-21 | data acquisition circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60104954U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6378227A (en) * | 1986-09-22 | 1988-04-08 | Chino Corp | Insulating circuit |
-
1983
- 1983-12-21 JP JP19701183U patent/JPS60104954U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6378227A (en) * | 1986-09-22 | 1988-04-08 | Chino Corp | Insulating circuit |
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