JPS54159852A - Binary circuit - Google Patents

Binary circuit

Info

Publication number
JPS54159852A
JPS54159852A JP6906778A JP6906778A JPS54159852A JP S54159852 A JPS54159852 A JP S54159852A JP 6906778 A JP6906778 A JP 6906778A JP 6906778 A JP6906778 A JP 6906778A JP S54159852 A JPS54159852 A JP S54159852A
Authority
JP
Japan
Prior art keywords
circuit
output
signals
binary
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6906778A
Other languages
Japanese (ja)
Inventor
Takashi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6906778A priority Critical patent/JPS54159852A/en
Publication of JPS54159852A publication Critical patent/JPS54159852A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Picture Signal Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain a floating threshold-system binary circuit which can converts alalogue signals by binary signals plurally, by performing the binary conversion of analogue signals by using sum signals of signals which have the same waveform and a fixed delay and a fixed advance respectively. CONSTITUTION:Output a of bias circuit 1 is supplied to the first delay circuit 5, and analogue signal a' which should be subjected to binary conversion is outputted, and the output of the first delay circuit is supplied to the second delay circuit 6. Output a of bias circuit 1 and output d of the second delay circuit are supplied to adder circuit 7 through the first attenuating circuit 8 and the second attenuating circuit 9 respectively, and threshold signal b is outputted. Output a' of the first delay circuit 5 and output b of adder circuit 7 are supplied to comparator circuit 4, and binary output c is transmitted.
JP6906778A 1978-06-07 1978-06-07 Binary circuit Pending JPS54159852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6906778A JPS54159852A (en) 1978-06-07 1978-06-07 Binary circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6906778A JPS54159852A (en) 1978-06-07 1978-06-07 Binary circuit

Publications (1)

Publication Number Publication Date
JPS54159852A true JPS54159852A (en) 1979-12-18

Family

ID=13391851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6906778A Pending JPS54159852A (en) 1978-06-07 1978-06-07 Binary circuit

Country Status (1)

Country Link
JP (1) JPS54159852A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59159034U (en) * 1983-04-09 1984-10-25 株式会社島津製作所 Binarization device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59159034U (en) * 1983-04-09 1984-10-25 株式会社島津製作所 Binarization device

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