JPS59157751A - Program counter control circuit - Google Patents

Abstract

PURPOSE:To reduce the number of steps of a program and improve the operation speed by stopping counting-up of the address in a program counter while the same instruction is executed for plural times. CONSTITUTION:Information indicating what times the same instruction should be executed repeatedly is written in a counter 3. A flip-flop 5 is set to stop temporarily a program counter 1. The program counter 1 is inhibited from incrementing by an output Q of a flip-flop 5. Contents of the counter 3 are decremented each time when one instruction cycle is executed. When a prescribed number of processings are terminated to generate a borrow output from the counter 3, the flip-flop 5 is reset. While the instruction is executed a required number of times, counting-up of the program counter 1 is inhibited with respect to hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program counter temporary stop circuit for use in an electronic computer with a built-in program.

In order to execute each instruction in a computer according to a predetermined order, the above instructions are RO'd in the above order.
The commands are stored in M (Read Only Memory) or 1-CRAM (Random Access Memory), and are sequentially read out and executed through a program counter, also called an address counter. In this case, generally the contents of the program counter are incremented by one each time one instruction is executed by an incrementer, so that the instructions are executed sequentially.

By the way, in electronic desktop calculators and other computers that process multi-digit numerical values, it is often necessary to execute the same instruction for each digit number when performing arithmetic processing of -. For example, to perform 95405231 +43159867, it is necessary to repeat the command 9 times, which is the sum of the corresponding digits, such as 1+7.3+6.

In this case, according to conventional arithmetic methods, the number of times an instruction needs to be executed is set by a program.

A method was adopted in which a set numerical value (necessary number of executions) was decremented by one each time the corresponding instruction was executed once, and the execution of the corresponding instruction was repeated until it reached 0.

By the way, in this case, in order to process -m, it is necessary to rewrite the program counter many times.
There are problems in that the number of steps required for the program increases and the calculation speed becomes slower.

To solve this problem, the number of steps in the program can be reduced by storing the required number of executions in advance and fixing the contents of the program counter at a fixed address while the number of executions is completed. is extremely effective. The present invention was made with this recognition in mind.
An object of the present invention is to provide a program counter temporary stop circuit that can fix the address of a program counter for an arbitrary number of times.An embodiment of the present invention to achieve the above object is a counter, a climenter, and a flip-flop. With the borrow (or carry) output of a counter that has circuitry and can be written to any number.

The circuit for incrementing (or decrementing) the program counter is controlled to stop counting the numerical value written in the counter until it reaches 7, and to release the stopping after the counting is finished. It is something.

The present invention will be explained below with reference to Examples.

FIG. 1 is a basic configuration diagram of a program counter temporary stop circuit according to an embodiment of the present invention. It is a 1μ program counter that stores an execution address address. This +
The program counter is rewritten each time one execution is completed by one operation, contributing to executing instructions in the order programmed into the RAM. Write any number in 3.

4 is a decrementer for decrementing the counter 3 by 1; 5 is a flip-flop circuit that is set by the set counter signal SC and reset by the borrow output from the counter; 6 is a RAM for storing a program;
This is an arithmetic circuit ALU that executes instructions retrieved from AM. The part shown at 8 becomes a program counter temporary stop circuit.

FIG. 2 is a time chart relating to the program counter temporary stop circuit, and the operation of the circuit will be explained with reference to this. For example, to fix the stored contents of the program counter for 9 instructions at a fixed address P+1, 9 instructions are written in the counter 3 in advance, and when the program counter is temporarily stopped, the flip-flop 5 is set by the set counter signal SC. and flip flop 5
Inhibit (1nhibit) the program counter l from being incremented by the output Q of j.

The prohibition continues until it is reset by a borrow output from the counter 3 side, that is, the 9 set in the counter 3 is decremented by 1 to become 8 at the first timing after the set counter signal SC force 1j is added, and then becomes 7. In this way, the contents of the counter are sequentially decremented by - every instruction cycle, and when it reaches -1, a borrow output occurs and the flip-flop 5 is reset.

In this way, the address of the program counter is fixed at a constant value for the required number of instruction cycles, and the same instruction is executed by hif! by hardware means for the number of digits! ! ,−
1 can be done. The number of program steps is therefore significantly reduced.

A comparison of the conventional case and the case according to the present invention with respect to the number of steps will be as follows.

Table 1 shows the state of the RAM before calculation.

Table 1 And RAM (0, Y) + RAM (2, Y) Y = 0~
Put the results of 8 into RAM (2, Y), Y = 0 to 8 and write in Table 2.
Do as shown below.

Table 2 In the past, such arithmetic processing was performed using the following program.

0.1-X, Y (X, Y l+(2, Y)- (2, Y), Yl1-Y (X, Y)+(2, Y)- (2, Yl, Yl1-Y (X, Y ) + (2, Y ), - (2, Y), Yl1-Y (X, Y) + (2, Y) - (2, Y), Yl 1-Y (X, Y) + (2, Y) - (2, Y), Yl1-Y (X, Y) + (2, Y) - (2, Y), Yl1-Y (X, Y) + (2, Y > - (2, Y) , Yl1-Y (X, Y) ten (2, Y) - (2, Y), Yl1-Y (X, Y) + (2, Y) - (2, Y), Yl1-Y That is, 10 instructions. The number of program steps required in the past.

However, according to the present invention, the address stored in the program counter can be fixed to a constant value, so the same arithmetic processing can be performed using the following three instructions.

0.1-X, Y SC9 (Set 9 on the counter) (X, Y) + (2, Y) - (2, Y), Yl1-Y In this way, the number of program steps is reduced to ⅓ or less.

The present invention u S -S (Storage - Stora
ge ) format and BCD operation can be executed in one instruction, and in this case, the conventional 3-R (Storage-Register)
Compared to the format, the number of steps is reduced to 1/10 or less, and the calculation time is reduced to about 1/20 or less.

FIG. 3(a) shows another embodiment of the present invention.

In this embodiment, one adder is used to increment the glogram counter 1 and the counter 3. That is, the adder is also used as an incrementer, focusing on the fact that when the program counter 1 is incremented, the counter 3 is not incremented, and when the counter 3 is incremented, the program counter 1 is not incremented.

The switching is performed by controlling the switch 8 using the output Q of the flip-flop 5. The naori counter 3 is a shift register type counter.

As explained above, according to one aspect of the present invention, the address stored in the program counter can be fixed as needed, and the instruction at the same address can be repeatedly executed an arbitrary number of times. Therefore, by adding a small number of hardware means, the number of program steps can be reduced, and the calculation speed can also be improved.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram showing one embodiment of the present invention, Fig. 2 is a time chart diagram, Fig. 3 (a) is a circuit diagram showing another embodiment of the present invention, and Fig. 3 (Fig. (a) It is a circuit diagram for explaining the circuit symbols in the figure. 1... Program counter, 2, 4... Climenter. 3... Counter, 5... Flip frog, 6...
・RAM, 7...ALU, 8...Switcher.

Claims (1)

[Claims] 1. Control the program counter and the program counter for controlling the arithmetic processing circuit? 1. A program counter control circuit comprising a control circuit for IJJ, wherein the operation of the program counter is controlled by the control circuit pressure in repetitive arithmetic processing.