JPS6017146B2 - computing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic device, and more particularly to a vector register consisting of M elements, a mask register consisting of M elements corresponding to each element of the vector register, and the vector register and mask register described above. and a vector length register indicating the length of the elements of the vector register, the elements of the vector register are taken out sequentially, and the elements of the vector register are divided according to the elements of the mask register corresponding to the number of elements specified by the vector length register. The present invention relates to an arithmetic device that performs operations on a computer.

As a control method for a computer that processes a large amount of vector data, a method is known in which a vector register is provided inside the processing device, data from a storage device is once transferred to the vector register, and then the arithmetic device is operated.

An overview of the operation of a computer that sequentially takes out elements of a vector register (VR) and performs operations between the elements will be explained.

Assume that the number of elements of the vector register (VR) is M=128, and the element numbers are assigned as 0, 1, 2, . . . , 127. The SUM command will be explained as an example of the operation.
The SUM instruction returns the corresponding vector register (VR) of the element number of the mask register (old M) whose element is not 0.
The sum of the elements is calculated for the number of elements specified by the vector length register (VL).

Figure 1 shows the vector register (VR) and mask register (
MR) configuration is shown. Set the element number to 0, 1, 2, ..., 12
7, expressed by a subscript, and the vector length is (VL) = 1
00, the non-zero elements of the mask register (old M) are set to MR.
, MR2, M old 4, . . . M crotch i, . . . MR mother. The total sum S to seek is S=VR, 10VR20VR40...10V
Ri+...10 VR spots.

The situation is shown in Figure 2. Vector register (V
The sum of the shaded portions of R) is what is sought. Here, if we look at the vector data, the outside of the vector data is “0”.
In addition to data in which significant data with a value of "0" is arranged continuously, there is also data in which a large number of data having a value of "0" are mixed together.

In the case of an arithmetic operation in which the result is the same even if the arithmetic operation is omitted for data having the value "0", in order to improve the arithmetic speed, conventionally, for example, the elements of the vector register are By doing things such as replacing the data, only significant data was collected before calculations were performed. Therefore, there was a problem in that the creation of the program became complicated. An object of the present invention is to solve the above problems and improve the calculation speed while making it easier to create a program. Therefore, the present invention provides a vector register consisting of M elements and each of the vector registers. A mask register consisting of M elements corresponding to the elements and a vector length register indicating the length of the elements of the vector register and the mask register are provided, and the elements of the vector register are sequentially taken out and the vector length register is specified by the vector length register. means for detecting that the contents of the vector length register are 0; and means for detecting that the contents of the vector length register are 0; means for detecting that the elements of the vector length register are 0, and when any of the means detects that the contents of the vector length register are 0 or that all the elements of the mask register are 0, the predetermined It is characterized by outputting the fixed results obtained.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 3 is a block diagram of an arithmetic unit according to an embodiment of the present invention, in which 1 is a vector register (VR), 2 is a mask register (old M), 3 is an address counter, and 4 is a
circuits, 5 to 7 are registers, 8 is an arithmetic circuit, 9 is a gate, 10 is a vector length register (VL), 11 is a -1 circuit, 12 and 13 are 0 detection circuits, 14 and 15 are AND circuits, 16 and 17 is an OR circuit. The operation when the above-mentioned SUM instruction is executed will be explained below.

When the SUM instruction is executed, vector register 1, mask register 2, and vector length register 10 are set by the previous instruction.
1 contains data necessary for calculation.

In addition, address counter 3, register 5, etc. have an initial value of “0”.
” is set.

At the start of instruction execution, the contents of the vector register 1 and mask register 2 are sequentially determined from the 0th element based on the address counter 3. Then, when the element of the mask register 2 is "1", the gate 9 is opened, the value output from the vector register 1 is set in the register 6, and the value of the register 5 is set as the value of the register 6 and the value of the register 5 is set in the arithmetic circuit 7. Add by.

The addition result is set in register 5 via register 7. The value of the address counter 3 is incremented every h by the eleventh circuit 4, and reading of the vector registers 1 and 1 and the mask register 2 continues. Further, when the element of the mask register 2 is "0", the addition operation is not performed and the next element is immediately read out.

On the other hand, the vector length register 10 is the vector register 1
Each time the mask register 2 is set, it is decremented by the 11 circuit 11. Then, when the value of the vector length register 10 becomes "0", the read operation and the addition operation are stopped. The value of register 5 is AND times 1
4 and the OR circuit 7. The above operation is performed when significant data exists in vector register 1. The value of vector length register 10 is “0” from the beginning.
”, or when the values of the mask register 2 are all “0”, the operation is as follows. When the value of the vector length register 10 is “0” from the beginning, the 0 detection circuit 13 It is detected that the value of the vector length register 10 is “0”, and “
Outputs 1”.

As a result, the AND circuit 15 is controlled and the fixed value (SU
In the case of the M instruction, “0”) is output from the OR circuit 17.
Then, the execution of the SUM instruction ends, and the process moves on to the next operation.

On the other hand, when the values of mask register 2 are all "0", the addition cycle by registers 5 to 7 and arithmetic circuit 3 is not executed, and the address counter 3 continues to input vector register 1 and mask register 2. will be carried out.

When all the elements of the length indicated by the vector length register 10 are read, if all the elements read from the mask register 2 up to that point are "0", the 0 detection circuit 12
outputs “1”. As a result, in the same way as when the value of the vector length register 10 is "0" from the beginning, the AND circuit 15 is controlled to a fixed value ("0" in the case of the SUM instruction).
) is output from the OR circuit 17. FIG. 4a shows an example circuit of the 0 detection circuit 12 shown in FIG.
is a flip-flop, 21 is an OR circuit, and 22 is an AND circuit.

Flipf. The input circuit 20 is set to an initial value of "0", and if all the data from the mask register 2 is "0", it is not set, and the AND circuit 22 outputs "1". FIG. 4b shows an embodiment of the 0 detection circuit 13 shown in FIG. 3, in which 23 is a NOR circuit and 24 is an AND circuit.

If the initial value of the vector length register 10 is "0", the AND circuit 24 outputs "1" at the calculation start timing. In addition, in the above embodiment, by slightly changing the circuit configuration, the state in which the values of the mask register are all "0" or the value of the vector length register is "0" is detected before the start of instruction execution, and the operation of the instruction is performed. Obviously, it is possible to terminate an operation without executing it to completion.

Furthermore, the circuit configurations of the address counters 3 and 11 circuits 4 and the vector length register 10 and -1 circuit 11 are similar, and can be realized by the same circuit, and are not limited to the above embodiment. . Furthermore, in setting the fixed value, a method may be considered in which registers 5 and 6 are set as initial settings for calculation. Naturally, the present invention can also be applied to a case where there are a plurality of vector registers and a plurality of mask registers by specifying one vector register and one mask register in each operation code. As described above, according to the present invention, when performing various operations using a vector register or a mask register as an operand, the contents of the vector register or mask register are in a special state, that is, the vector length is 0 or the mask register is This eliminates the need for programs to be aware of the state in which all elements are 0, resulting in the excellent effect that programs can be created easily and efficiently.

[Brief explanation of the drawing]

Fig. 1 shows the configuration of the vector register and mask register, Fig. 2 shows an example of addition, Fig. 3 is a block diagram of an arithmetic unit according to an embodiment of the present invention, and Fig. 4 shows an example of a 0 detection circuit. This is an example circuit. In the figure, 1 is a vector register, 2 is a mask register, and 3 is a vector register.
5 is an address counter, 5 is a register, 8 is an arithmetic circuit, a single vector length register, 12 and 13 are 0 detection circuits, and 20 is a flip-flop. Kotobuki's younger brother Otoma 3 crabs 4th illustration

Claims (1)

[Claims] 1. A vector register consisting of M elements, a mask register consisting of M elements corresponding to each element of the vector register, and a vector length register indicating the length of the elements of the vector register and mask register, In an arithmetic unit that sequentially takes out the elements of the vector register and executes an operation between the elements of the vector register according to the elements of the mask register corresponding to the number of elements specified by the vector length register, means for detecting that the contents of the vector length register are 0, and means for detecting that all elements of the mask register are 0; An arithmetic device that outputs a predetermined fixed result when a state in which all elements of a mask register are 0 is detected.