JPS5668863A - Operating device - Google Patents
Operating deviceInfo
- Publication number
- JPS5668863A JPS5668863A JP14525279A JP14525279A JPS5668863A JP S5668863 A JPS5668863 A JP S5668863A JP 14525279 A JP14525279 A JP 14525279A JP 14525279 A JP14525279 A JP 14525279A JP S5668863 A JPS5668863 A JP S5668863A
- Authority
- JP
- Japan
- Prior art keywords
- register
- contents
- vector
- circuit
- detected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To generate programs easily and efficiently, by making it unnecessary to be conscious of contents of the vector register or the mask register in case that contents of these register are used as operands to perform various operations. CONSTITUTION:Vector register 1 of M-number elements and mask register 2 of M-number elements corresponding to register 1 are provided, and further, vector length register 10 to indicate the length of elements of registers 1 and 2 is provided. Contents of register 10 are detected by 0 detecting circuit 13, and it is detected by 0 detecting circuit 12 that contents of register 2 are all 0. Operation between element of register 1 is executed according to the element of register 2 corresponding to the element designated by register 13 by operating circuit 8; and when 0 detecting circuits 12 and 13 detect the 0 state, the predetermined fixed result is output from OR circuit 17 to facilitate generation of programs.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54145252A JPS6017146B2 (en) | 1979-11-09 | 1979-11-09 | computing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54145252A JPS6017146B2 (en) | 1979-11-09 | 1979-11-09 | computing device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5668863A true JPS5668863A (en) | 1981-06-09 |
JPS6017146B2 JPS6017146B2 (en) | 1985-05-01 |
Family
ID=15380825
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54145252A Expired JPS6017146B2 (en) | 1979-11-09 | 1979-11-09 | computing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6017146B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61136943U (en) * | 1985-02-18 | 1986-08-26 |
-
1979
- 1979-11-09 JP JP54145252A patent/JPS6017146B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6017146B2 (en) | 1985-05-01 |
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