JPS59154547A - Instruction readout control system - Google Patents

Abstract

PURPOSE:To read following instructions in succession to a readout of an instruction at a branch destination by adding an adding function for instruction readout width to an adder which is used to calculate a branch destination address. CONSTITUTION:A branch instruction is inputted to an instruction register 4 and the value of its displacement field is selected by selectors 16 and 17 and inputted to the adder 5. Consequently, the address of the branch destination is calculated and inputted to a register 6. The branch destination address inputted to the circuit 6 is transferred to a storage device 1 to read the 1st instruction at the branch destination and the address calculated by adding eight bytes as instruction readout width to the branch destination address is held in the register 6. Then, the 2nd instruction at the branch destination is read out by said address. Further, the adder 8 adds readout with corresponding to two instructions at the branch destination to read the 3rd instruction. Similarly, said operation is repeated to generate readout addresses successively by the adder 8, and read-out of the instructions excecutes successively.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a synchronized reading control method for an information processing device, and includes an adder used in calculating a branch destination address and an adder used in continuous instruction reading. This article concerns the command readout and control method when the devices are provided independently.

[Prior art]

Generally, in a 1n information processing device, an adder (A: Addt"f
~Adtier) and an adder (A I: klciresy In) used when issuing consecutive instructions.
cremen, ier). That is, when the operand address of the instruction and the instruction address of the branch destination (rjl, A, A are used to find it, and the consecutive instructions that follow it are read out, d5, using AI, the actual execution Nakajima-dai's - )′ Add the constant σ) instruction read width to the trace to find the bottle removal address of the next instruction. By creating a piece of music for this AI and AA configuration, the command presetting control and the initialization/processing can be easily accomplished.

By the way, in the case of such a 1N information processing device a, the branch 517 instruction is deco~1.sa? When L, the branch destination address τ is determined by A and A, and at the same time, the second cycle VC Oi- (branch destination V) island is set up and transferred to the branch destination -71-res iAI.
, 8↓, the subsequent instruction at the branch destination is read and an at[/s] is generated in the next cycle (one cycle after another) of the upper a self-next cycle. For this reason, after the branch destination address of the branch instruction is generated, there is a one-cycle gap until the read address of the subsequent instruction at the branch destination υ is found. The disadvantage was that it was not possible to
In cycle 2, the branch destination instruction is read, and in cycle 4, the instruction next to the branch destination is removed, and it is determined that the second cycle 3 of the master is vacant, resulting in -2.

[Purpose of the invention]

An object of the present invention is to provide an information processing device V ( The object of the present invention is to provide an instruction read-out system in which, following the read-out of a branch destination instruction, the start of subsequent instructions is i+-.

[Direct essentials of the invention]

The present invention adds an instruction read width l'41 and f function to A, and after calculating the branch destination address specified by the branch instruction, reads the branch destination instruction and AAV
Here, the next instruction read address is obtained by adding the instruction read width to the branch destination address, and the next instruction is immediately read in the cycle following the read cycle of the branch destination instruction, and the subsequent instruction read address is calculated. It is characterized by using KAI.

[Embodiments of the invention]

FIG. 2 shows a configuration diagram of an embodiment of the present invention. In Figure 2, note 1. Commands and operands are stored in the device 1, and a predetermined byte of data specified by the address line 5 or 15' can be read out to the data line '20. The instruction buffer 2 is a register for temporarily storing instruction data (hereinafter, instruction read width is 8 bytes) read from the storage device 1, and is composed of two 8-byte registers.

The shifter 8 shifts the next instruction to be decoded to the left and transfers it to the instruction register 4.

The instruction register 4 fetches instructions one by one from the instruction buffer 2 via the shifter 3, decodes the instructions and stores the operands (in 1, the instruction is held).

The instruction field consists of an operation field, a register address field, and a displacement field.

k % L/ The operation field of Sister Li's command is input to the decoder 10 via data line 2]. The decoder]() sets the operation field fWHa of the instruction and outputs "1" to the signal line 26 for one call of the branch instruction. 1.1 to 14 are Noritsubu flop groups,
When the signal line 26V is output, it serves to shift the "1" signal at a cycle pitch, overlapping each other by half a cycle.

The register address field of the instruction register 4 is transmitted to the general-purpose register 25 via the data line 22, and the contents of the general-purpose register specified by the instruction are extracted to the data line 2i3. The contents of the data line z8 pass through the selector 16 and become one input of the adder 5.

The other input of the input device 5 is the one in which the value of the displacement field of the instruction is given through the data line 24 and the selector 17.
Ru. Find the operand address of an instruction or the branch destination address of a branch instruction
AA), and when the output of the free lag flop 12 is "0", the selector 16 . ], add the values of the displacement field of the general register z5 selected by 7 and the displacement field of the instruction register li,
The operand address or branch destination address specified by the instruction is calculated and output to the register 6t. On the other hand, when the output of the flip-flop 12 is 1'' (ri,, selector 16u-y' address iff N, the contents of register (5) holding the result are selected via the gate line 27. is fixed 1) Selects the white "8" and inputs these to the adder 5, so in the adder 5, 18" is added to the address counter-n result obtained in the cycle i1. 11
, stored in register O. In register 6? 1 is transmitted to the memory device surface ↓/\ via the address line 15 as a read address.

The adder 8 is an adder (AI) that continuously outputs instructions and calculates the output address of the next instruction. This adder 8 is configured so that the output of the flip-flop 14 is "O".
"When r" 1, d in register 7, -7 register 19
Add the fixed value "8" selected by t and read the next instruction 11X sear address? It is stored in register 7 again through all intermediate registers 9. On the other hand, 1,7 Lituzov (J
When the output of the third knob is l'', adder 8 selects the fixed value (tl''16'' selected by selectors J and 9) to the contents of register 7.
Old storage. The contents of this register 7 are also transmitted to the a[co-storage device ffl by reading [7].

The selector 1111 selects the input data to the register 7. When the output of the flip-flop 12 is "(l"), the output of the intermediate register 9 is valid, and the output of the flip-flop 12 is "1". In this case, the output of register 6 is made into a ringing sound.

Next, the operation of the branch sub-board, which is the load of the present invention, at the time of command 1 and output 1 will be explained with reference to the time chart shown in FIG.

When a branch instruction is input to the instruction register 4, the γ coater ↓0 sets the 1st line 213 to 1, and as a result, the 11th to 1st moves are shown in Figure 8. In cycle 1, the output of the flip-flop 113 is "0", so the output of the general-purpose register 25 specified by the register address field of the instruction register 4 and the instruction register are The value of displacement field 4 is selected by selector 1.6.1-7 and becomes the input to adder 5.

From this tLK, the branch destination address is 81n in adder 5.
-1 result is transferred to 1-' distalo.

The branch destination address of this register 6 is transmitted to the storage device ]- by the address line 15 in the next cycle 2, and the first instruction reading 7 of the branch destination is performed.

At this time, the output of flip-flop 1z is V","1"'7
(Since the contents of l/distalo fret are transferred to register 7 VC through selector 18, the branch destination address is held in register 7. In cycle 2 with father, (dl flip knob) Since the output jJ of 2 is J'', the inner diameter of the register 6 and the fixed 1st straight "8" are selected by the selector 16.17, resulting in /la 8450 manpower.In this way, at the end of cycle 2, The address obtained by adding the instruction read width of 8 bytes to the branch destination address is held in l/distaro.

In the next Daikuru 3, the register h marked 6 VC is held.
The address is transmitted to the storage device 1 via the address line 15.
Then, the second instruction at the branch destination is read. −
In this cycle δ, the output of the flip knob 14 becomes “1”, so the selector 19 sets the fixed value “16”-t
a<select, add)9. In cycle 3, the branch destination address held in register 7 and the identification value "16°" (read width for 2 instructions) are added in cycle 8Qζ.
The output of the ZudeV flip-flop 18 becomes "0" -
(Therefore, the application result of the timer 8 is input to the write register 7 via the middle 114.I register 9 and the selector 18.

In the next cycle 4, the address held in the +14[F register is transmitted to the storage device 1 by address @ i 5', and the 8th instruction at the branch destination is read (~ is EJ'. Same as +911C, In this cycle 4, the output of the flip knob 14 is "O" V (selector if it is not set to C), GNd fixed value "8" is selected, υo# is added to device 8, and the contents of registers 7 are selected. The fixed value "8" is added to
The binding is input into the tl register 7. Therefore, in the next cycle 5, the instruction reading for the fourth branch destination is performed depending on the contents of the 17';' stuff. At the same time, add →
, I go back to device 8 and find that the fixed value 08” is in the contents of register 7.
The value is calculated and the register 7 is filled in. Thereafter, the same operation is repeated, the adder 8 continuously generates the read address of the -C instruction, and the instruction is successively read out.

As described above, the read address of the instruction after branching is generated in cycle L2.8.4...J series 17gL, and as a result, the instruction readout after branching is also generated in cycle 2.
, i3.4.5... are continuously lit.

〔Effect of the invention〕

According to Honmen Akira, reading the branch destination instruction of a branch instruction] 7 and reading the next instruction can do anything consecutively, so after 2Δ after branching with a branch instruction, the branch destination instruction or the subsequent instruction 71,000 is not read into the instruction buffer, the probability that the start of instruction decoding will be delayed is reduced, and the performance of the information processing device is improved.3.

[Brief explanation of drawings]

The J-diagram is the command readout from r to 1j Mitoj formula ke/C's timing/gu diagram, the 21st \I is Kizo et al + Jj
6) There is a configuration diagram of one embodiment, Figure 3 (see Figure 2). There is a timing chart for explaining the construction as shown in Figure 2. instruction buffer; 3
...Insert, 4...Instructor/Jister, 5...First adder, 8...Second adder, 1-0...Decoder, 1
1~14-...Flip-flop, 15.15'...
・Address line, 16-19)... Yarekuta. Wallet IReso 5-F'' Patent attorney Makoto Suzuki □A FM Procedural Correction FM (Voluntary) Income [River + (Amount 0 yen Showa June 2019 Canada Day 2, Name of invention f's, Command read control method 3, Supplement 1)
1:Relationship with the person and 1ift For the applicant==Shouting name (510) Hitachi, Ltd. Tsukushiki #4, Agent [Sou] 151 fi Address Kogej119 Shibuya [Meyoyogi] 2T'r
-138th 12th race) Cotton A1" Bee L, 201shi J5
Supplement i [Number of inventions increased by None 6, Supplement II:
, Subject matter of the "Claims" column 7 of the description, Contents of the amendment The statement of the claims of the description is supplemented as shown in the attached sheet. 8. List of attached documents Document stating the scope of patent claims iI'++
1 claim +l+ A first adder that calculates a branch destination instruction address specified by a branch instruction, and a second adder that sequentially calculates an instruction read at 1/s when reading consecutive instructions. In an information processing device in which the first adder is provided with an instruction read width adding means, and after the first adder calculates a branch destination instruction 1 address, using the first adder, Instruction reading characterized in that the next instruction read address of the branch destination instruction is obtained by adding an instruction read width to the branch destination instruction address, and subsequent instruction read addresses are generated using the second adder. control method.

Claims (1)

[Claims] (1) Information in which the first adder, which calculates the instruction address of the branch destination specified by the branch instruction, and the second adder, which sequentially obtains the instruction read address when reading seven consecutive instructions, are independent. In the processing device, an instruction read 1 is sent to the first adder.
-27 width addition means is provided, and after the first adder calculates the instruction address of the branch destination, the first addition stagnation is used to add an instruction read width of 17 to the instruction address of the branch destination i1. In addition, the instruction read system i'1j is characterized in that an instruction +1 output address next to the branch destination instruction is obtained, and subsequent instruction read addresses are generated using the first adder.
ll power formula.