JPS60168237A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To perform arithmetic at a high speed by adding a decoder and selecting data during decoding of instructions. CONSTITUTION:An arithmetic unit is provided with a decoder 11, and an address signal of an instruction register 1 is received by the decoder 11 in an instruction fetch operation cycle, and control signals are sent to selectors 4 and 5. The selector 4 is controlled by the decoder 11 in accordance with the signal from the instruction register 1 simultaneously with an instruction decoding cycle, and control signals of a general register 6 and a program memory 7 are selected by selectors 4 and 5 and are sent to operation registers 8 and 9. An instruction decoder 2 istructs the microprogram memory 7 the decoding operation to generate a control signal in a microprogram memory 3, and an arithmetic logic operation circuit 10 is controlled, and the signal of the data fetch operation is operated in an operation execution cycle by the operating circuit 10, and the result is stored.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an arithmetic device for prefetching arithmetic instructions.

[Step 1] Figure 1 is a block diagram showing a conventional arithmetic unit. In Figure 1, (1) is an instruction register, and (2) decodes an address signal output from the operation code of the instruction register (1). An instruction decoder (3) is a microprogram memory that receives the address signal decoded by the instruction decoder +1) and generates each control signal; (4)
(5) is a selector which inputs the address signal of the instruction register (1) and the control signal of the microprogram memory (3);
), (6) is a general-purpose register that receives the output signal of selector (4), and (7)
) is a program memory whose input is the signal of the selector (5), (8) is an arithmetic register whose input is the signal of the general-purpose register (6), and (9) is the program memory (
The arithmetic register OQ which receives the signal of 7) is an arithmetic logic circuit which receives the control signal of the microprogram memory (3) and the signals of the arithmetic register (8) and the arithmetic register (9).

2 shows the operation waveforms of FIG. 1, in which (A) is an instruction fetch operation cycle, (B) is an instruction decode cycle, (C) is a control signal generation cycle, (D) and (K) are data fetch operation cycles, (F) is an operation execution cycle, (G) is a result storage cycle, and (10) - (t represents time.

Next, the operation will be explained. (tl) indicates that the execution contents are executed in the instruction register (7 operations per input).

At (t2), the instruction decoder (2) outputs the instruction register (1).
It receives the microprogram from 1 and performs decoding operation.

Stored in microprogram memo January 3), (tS)
A control signal is sent from the microprogram memory (3) to the arithmetic and logic operation circuit α1 and selectors (4) and (5).

(At t, the address signal from the instruction register +11 is selected by the selector (4), at (tS), the displacement from the instruction register (1) is selected by the selector (5), and at (t6), the arithmetic logic operation circuit Execute the calculation in a1.

At (tl), the result is stored in the general purpose register (6) or the program memory. However, as mentioned above, the instruction fetch operation cycle (■) and the instruction decode cycle (B)
, control signal generation (C), data fetch operation (D), and (IC) are sequentially processed to perform an operation error cycle (or) and a result storage cycle (G).

The above instruction fetch operation cycle (A), instruction decode cycle (B), control signal generation cycle (C), data fetch operation cycle (D) and (E), operation execution cycle (F), result storage cycle (() ) for the first time since the instruction decode cycle (B) at t (70) (tS)
At (t4), data fetch operation cycles (D) and (K) are performed.

This has the disadvantage that it takes time to start calculations.

[Summary of the invention]

The present invention was made with the aim of improving such drawbacks, and by adding a decoder to an arithmetic unit, data is selected while an instruction is being decoded, thereby shortening the preprocessing time of an arithmetic operation.

As a result, we propose an instruction prefetching arithmetic device that can repeat operations at high speed.

[Embodiments of the invention]

FIG. 3 is a block diagram showing one embodiment of the present invention.

The instruction register (1), instruction decoder (2), microprogram memo (January 3), general-purpose register (6), program memory (7), arithmetic registers (8) and (9), and arithmetic and logic circuit members are conventional devices. are exactly the same.

αD is a selector whose control signals are an address signal for the instruction register +1) and a signal from the decoder aυ.

FIG. 4 shows the operating waveforms of FIG. 3.

(Al is the instruction fetch operation cycle, (B) is the instruction decode cycle, (C) is the control signal generation cycle, (D)
and (E) is a data fetch operation, and (F) is an operation execution cycle.

(G) shows the result storage cycle.

A signal is sent to the instruction register +11 in the instruction fetch operation cycle (A), and the address signal from the instruction register fl) is decoded in the instruction decode cycle (2).

Further, the address signal of the instruction register tl) is received by the decode αB, and a control signal is sent to the selectors (4) and (5).

Also, at the same time as the instruction decode cycle (B), the signal from the instruction register (1) is sent to the selector (
4), selectors (4) and (5) select the control signals of the general-purpose register (6) and the program memo (January 7), and send them to the arithmetic register. The instruction decoder (11
1 causes the microprogram memory (7) to perform decoding.

The microprogram memory (3) generates a control signal to control the arithmetic and logic operation circuit Ql, and the data fetch operation CD) and (F) signal is sent to the arithmetic and logic operation circuit 11 to perform an operation execution cycle (F). )L, store the result.

〔Effect of the invention〕

As explained above, this invention has a simple structure in which a decoder is added to an arithmetic unit, so that a selector can be controlled by a signal from the decoder, and data can be fetched while a signal from an instruction register is being decoded. This has the effect of allowing high-speed calculations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional arithmetic device, FIG. 2 is a diagram showing operating waveforms of the conventional arithmetic device, and FIG. 3 is a block diagram of a arithmetic device showing an embodiment of the present invention. FIG. 4 is an operational waveform diagram of an arithmetic unit showing an embodiment of the present invention. In the figure, +1) is an instruction register, (2) is an instruction decoder, (3) is a microprogram memory, (4) and (
5) is a selector, (6) is a general-purpose register, (7) is a program memory, 181 and (9) are arithmetic registers, α
Q is an arithmetic logic operation circuit, and αυ is a decoder. Also(
A) is an instruction fetch operation cycle, and (B) is an instruction decode cycle. (0) is a control signal generation cycle, (D) and (K) are data fetch operation cycles, (F) is an operation cycle, (
G) is the result storage cycle, (to) to (to represents time. The same or equivalent parts in the two figures are indicated by the same reference numerals. Agent Masuo Oiwa Figure 1

Claims (1)

[Claims] an instruction register that holds execution contents; an instruction decoder that receives a signal from the instruction register; a microprogram memory that receives a signal from the instruction decoder; a signal from the instruction register; a selector that receives the instruction register signal; a general-purpose register that receives a signal from the selector, a program memory that receives a signal from the selector, an arithmetic register that receives a signal from the general-purpose register, an arithmetic register that receives a signal from the program memory, and an arithmetic logic operation that receives a signal from the arithmetic register. An arithmetic device characterized by being equipped with a circuit.