JP2000181714A - Instruction controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mount a work register without increasing hardware quantity. SOLUTION: The update holding indication of an operand and the register update buffer address of the operand are stored in an update table 22 by individual operands. The addresses of the register update buffer are made to correspond to the update holding indication and the register update buffer address, which are stored in the update table 22. They are written into a reservation station 33 and the register update buffer is used as a work register in accordance with the update holding indication.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction control apparatus which enables an out-of-order instruction execution to execute instructions at a high speed in an information processing apparatus.

[0002]

2. Description of the Related Art Here, out-of-order instruction execution is a processing method in which an instruction having input data is executed at any time in an order different from the instruction order specified by a program. Execution is in any order, but instructions must be executed as if resources accessible from the program, ie, storage areas, register contents, etc., were updated and referenced in program order.

There is a register renaming technique as a technique for ensuring that register contents are updated and referenced in a program order. In the conventional register renaming technique, a register update buffer is assigned to an instruction to update a register, and an instruction to perform subsequent register reference refers to the assigned register update buffer instead of the register.

An update pending instruction bit is registered on the reservation station which issues the instruction, and the register or the register update buffer is selected by the update pending instruction bit. The data in the register or buffer thus selected is used as source data. As described above, efficient hardware was used as a mechanism for operating simple instructions at high speed. On the other hand, it is desirable that a complicated instruction such as updating and referring to a plurality of resources in a plurality of machine cycles is executed at a certain speed by efficient hardware. When such a complicated instruction is executed, the execution speed greatly differs depending on whether there is a work register that can be referred to at high speed.

Here, a conventional instruction control device will be described. FIG. 12 is a diagram for explaining the operation of a conventional instruction control device, and specifically shows an example of a register renaming technique. In FIG. 12, an update buffer address table and a register update suspension table that constitute the update table 22 are indexed from the logical register address (R) on the instruction register 20, and a register update buffer address and an update suspension instruction are read out. The read information is registered on the reservation station 40. The general-purpose register (GPR) 42 and the register update buffer (RUB) 44 are indexed by the address read from the reservation station 40, and the indexed information is sent to the arithmetic unit 35. The work register (WR) 46
Stores source data and instruction execution results.

FIG. 13 shows a reservation station 40.
It is a figure showing the example of. In FIG. 13, P1 and P2 are first and second operand update pending instructions, RA1 and R2, respectively.
A2 indicates the first and second operand general-purpose register addresses, respectively, and UBA1 and UBA2 indicate the first operand register update buffer addresses, respectively. GPR42 is read if P1 is on, RUB4 if P1 is off
4 is read. The reservation station 40 stores an operand update pending instruction, an operand general register address, and an operand register update buffer address in association with each entry and for each of the first and second operands.

FIG. 14 is a diagram showing an example of a reservation station in which an address for the WR 46 is additionally registered. In FIG. 14, reference numeral 41 denotes a reservation station obtained by modifying the reservation station 40, and WA1 and WA2 denote first and second operand work register addresses, respectively.

FIG. 15 is a diagram for explaining a load (L) instruction and a compare (C) instruction in the configuration of FIG.
6 is a diagram for explaining the contents of the update table, and FIG.
FIG. 4 is a diagram showing an example of an entry of a reservation station 41. In FIG. 15, L instruction is, for example, GP
R (3) (“3” is the entry number) is RUB (4)
(“4” is an entry number) and is updated. The C instruction follows the L instruction and compares GPR (3) with GPR (4). When the decoding of the L instruction is completed, the update buffer address table and the register update pending table are updated in the update table 22, as shown in FIG.

That is, GPR (3) is renamed to RUB (4), and the update pending instruction P1 of GPR (3) is “1”. When the decoding of the C instruction is completed, the reservation station 41 in which the C instruction is generated is obtained as shown in FIG. That is, the first
As an operand instruction, since P1 is "1", RU
B (4) is used, and as the second operand instruction, GPR (4) is used because P2 is 0 (zero). Since the C instruction is a simple instruction, WA1 and WA2 are not used. FIG.
At the timing of (a), RUB (4) and GPR (4)
Are read, sent to the arithmetic unit 36, and compared.

[0010]

However, as in an information processing apparatus which does not employ the conventional register renaming technique, a general-purpose register and another work register, and a dedicated address for accessing the work register are used. If it is implemented separately, the amount of hardware will explode. Therefore, there has been a demand for a method of realizing an efficient and high-speed working register without increasing the amount of hardware.

The present invention provides an instruction control apparatus capable of mounting work registers without increasing the amount of hardware in an information processing apparatus that performs register renaming in order to solve the above-described problem of the conventional example. The purpose is to do.

[0012]

Means for Solving the Problems The above-mentioned problems are solved,
In order to achieve the above object, an instruction control apparatus according to the present invention includes a reservation station, a table for storing operand update pending instructions and operand register update buffer addresses for each operand, and a register for storing instruction execution results. An update buffer, means for designating an update buffer address, means for designating an update suspension instruction, and means for selectively storing these designated outputs in the reservation station are provided.

According to the first aspect of the present invention, the update pending instruction of the operand and the register update buffer address of the operand are stored for each operand in the table, and the update pending instruction and the register update buffer address stored in the table are stored. Control of writing to the reservation station by associating the address of the register update buffer with the address of the register update buffer, so that the register update buffer can be used as a work register, thereby implementing a work register without increasing the amount of hardware It is possible to do.

According to a second aspect of the present invention, in the first aspect of the present invention, the register update buffer is provided when an update suspension instruction written in the reservation station under the control of the control means is in an off state. Further comprising a general-purpose register for storing an instruction execution result according to the address of the instruction and whether or not the instruction execution result is written.
An address for supplying data for updating the designated general-purpose register is compared with a previous address of the register update buffer stored in the reservation station, and a match is detected in the reservation station. The update pending instruction is turned off to complete the update of the specified general-purpose register, and information indicating that the register update buffer in which data is stored is for work is stored in the reservation station, and the register is updated. When the update buffer is for work, it is characterized in that the update hold instruction in the reservation station in which a match is detected is held in an ON state.

According to the second aspect of the present invention, information indicating that the register update buffer storing data is for work is stored in the reservation station. , The update pending instruction in the reservation station in which the is detected is held in the ON state, so that the register update buffer can be used as a work register, thereby implementing the work register without increasing the amount of hardware. It becomes possible.

According to a third aspect of the present invention, in the instruction control device according to the second aspect of the present invention, the general-purpose register is connected to a stage subsequent to the register update buffer, and the register update buffer is connected to a working data storage register. If specified, the register update buffer is prevented from being assigned to an instruction for updating the general-purpose register.

According to the third aspect of the present invention, the general-purpose register is connected to the subsequent stage of the register update buffer, and when the register update buffer is designated as the working data storage register, the instruction for updating the general-purpose register is provided. Since the allocation of the register update buffer has been suppressed,
The register update buffer can be used as a work register, which makes it possible to implement the work register without increasing the amount of hardware.

According to a fourth aspect of the present invention, in the instruction control device according to the second aspect of the present invention, only a specific number can be designated as the work register address, and the general-purpose register is updated. When assigning a register update buffer address to an instruction, it is characterized in that an address other than the specific number is assigned.

According to the fourth aspect of the present invention, only a specific number can be designated as a work register address, and when a register update buffer address is assigned to an instruction for updating a general-purpose register, a specific register update buffer address is assigned. Since the numbers other than the numbers are assigned, the register update buffer can be used as a work register, and thus the work registers can be mounted without increasing the amount of hardware.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an example of the configuration of an instruction control device according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes an instruction control device (CPU). The instruction control device 10 includes, for example, an execution unit (EU) 11, an instruction control unit (IU) 12, and a storage control unit (SU) 13, as shown in FIG.

The storage control unit 13 is provided with a buffer storage unit 14 for temporarily storing data and the like. The execution unit 11 is a unit that performs an operation such as an arithmetic operation, a logical operation, and an address calculation, and the storage control unit 13 stores data operated by the execution unit 11.

The instruction control unit 12 controls execution of instructions of a program.
And control of processing for causing the execution unit 11 to transmit necessary data to the execution unit 11 and storing the operation result performed by the execution unit 11 in the storage control unit 13, and a method out of order (out-of-order method) In, the control of the execution order of the instructions is also performed.

FIG. 2 is a partial configuration diagram of the embodiment of the present invention, and is a diagram for explaining an operation when a general-purpose register is updated. In the present embodiment, the general-purpose register 26
Is updated, the newly provided update table 22
And the register update buffer 25. The update table 22 registers an update buffer address table 29 in which addresses of a plurality of register update buffers 25 corresponding to the general-purpose registers are registered, and an update suspension instruction bit indicating whether or not the update to the general-purpose registers 26 is suspended. And a register update pending table 28.

In this embodiment, the register update buffer 25 temporarily stores the result of the instruction execution when executing the instruction, and stores the instruction execution result in the general-purpose register 26 when the instruction execution is completed. It is used for storing, and a plurality (in FIG. 2, represented by one block) is provided.

An instruction of a program executed by the instruction control device 10 of FIG. 1 is fetched from a memory (not shown),
When stored in the instruction register 20 in the instruction control device 10, the logical address of the general-purpose register 26 is output from the instruction register 20 to the decoder 21. This is called decoder 21
To update the register update pending table 28.

The update buffer address table 29 indicates which register update buffer 25 (or which register update buffer 25
This is a table in which an update buffer address indicating whether or not the update buffer is stored is associated with the number (or address) of the general-purpose register 26 and stored. The register update pending table 28 is a table in which an update pending bit indicating that the general-purpose register 26 is in an update pending state is stored in association with the number (or address) of the general-purpose register 26.

Further, the update pending instruction bit of the entry of the register update pending table 28 corresponding to the physical address of the general-purpose register 26 sent from the decoder 21 is 1
Is set to indicate that the update of the general-purpose register 26 is suspended.

The register update buffer 2 receiving the address of the register update buffer 25 from the update table 22
5 is an execution unit 11 or a storage control unit 13
Operation result or read result 24 (see FIG. 1)
And the data 24 is stored in the corresponding address.

At this time, the update buffer address used for writing into the general-purpose register 26 is output from the register update buffer 25 and sent to the comparator 23. on the other hand,
The comparator 23 compares each address of the update buffer address table 29 with the address currently sent from the register update buffer 25. If there is a matched address, the register update corresponding to the address is suspended. The update pending instruction bit in the table 28 is reset to “0”.

The address comparison in the update table 22 shown in FIG. 2 is performed by hardware, and a physical address corresponding to a logical address is output from the update table 22. In addition, data is read not from a general-purpose register (physical register) having a large physical quantity but from a register update buffer of the present invention having a small physical quantity.
Therefore, the number of logic stages of circuits such as a selector and a logic circuit for data transfer is reduced, the frequency of machine cycles can be increased, the execution time of each stage of the pipeline can be shortened, and the instruction control device can be controlled. 10 can be speeded up.

FIG. 3 is a partial configuration diagram of the present embodiment, showing the configuration and operation at the time of register reading. In the present embodiment, in addition to the above-described update table 22, a general-purpose register address, a register update buffer address corresponding to the general-purpose register 26 (output of the update buffer address table 29), and an update pending instruction bit of the general-purpose register 26 Is stored.

When the instruction is decoded, the general-purpose register 26 from which data is read by the instruction is detected by indexing the register update pending table 28 to determine whether the update is pending by the preceding instruction.
The data in the general-purpose register 26 is read. Then, as soon as the instruction is decoded, the instruction is dispatched to the execution unit (arithmetic unit 35). On the other hand, if the update is pending, the general register address and the register update buffer address corresponding to the general register 26 and the general register 2
6 is stored in the reservation station 33 when the instruction is decoded, and when the register update buffer 25 becomes available, the data in the designated register update buffer 25 is read out and the instruction is executed from the reservation station 33. Dispatch to unit 11.

With the above-described mechanism, an out-of-order instruction can be executed without delay of a machine cycle.

When the execution of the update instruction of the general-purpose register 26 is completed, the address of the register update buffer 25 for supplying data for updating the general-purpose register 26 and the address registered in the update buffer address table 29 are stored. By comparing with all the register update buffer addresses and resetting the update pending instruction bit in the register update pending table 28 corresponding to the register update buffer address for which a match is detected, the completion of the update of the general purpose register 26 is confirmed. To instruct.

Similarly, when the execution of the update instruction of the general-purpose register 26 is completed, the address of the register update buffer 25 for supplying data for updating the general-purpose register 26 and all the addresses registered in the reservation station 33 are stored. By comparing with the register update buffer address and resetting the update pending instruction bit in the reservation station 33 corresponding to the register update buffer address where the match is detected, it indicates that the update of the designated general-purpose register has been completed. I do.

First, when a register read instruction is issued, a logical address of a general-purpose register is output from the instruction register 20, and the logical address is decoded by the decoder 21. An entry of the update table 22 corresponding to the decoded general-purpose register address is searched, and an entry of the register update pending table 28 corresponding to this address is obtained.

Next, an update pending instruction focus is read from the entry of the register update pending table 28, and when this is "0", a general register address corresponding to the general register 26 is given, and data corresponding to this address is given. The content is input to the arithmetic unit 35. This is because when the update pending instruction bit is “0”, the general-purpose register 26
Indicates that the data content of has been updated,
Data is input from the general-purpose register 26 to the arithmetic unit 35.

If the update pending instruction bit in the register update pending table 28 corresponding to the physical address of the general purpose register 26 output from the decoder 21 is "1", the register update buffer address table corresponding to the pending instruction bit The address of the register update buffer 25 in 29 is output to the reservation station 33.

In the reservation station 33, the column 30 is stored based on the information sent from the update table 22.
, An update pending instruction bit, a column 31 for register update buffer addresses, and a column 32 for general register addresses. Then, the reservation station 33 gives priority to the execution order of each register read instruction in consideration of the above-mentioned three pieces of registered information and the like, and executes the instruction in the order of data.

Data is read from the register update buffer 25 based on the register update buffer address sent from the reservation station 33, and the data is input to the arithmetic unit 35. Next, general-purpose register 2
6 is issued, the register update buffer address of the data input to the arithmetic unit 35 is sent from the register update buffer 25 to the comparator 34. On the other hand, from reservation station 33, column 3
The register update buffer address for each entry of 1 is output and they are also sent to comparator 34. Comparator 3
When the coincident register update buffer address is detected in step 4, the update pending instruction bit corresponding to that address in column 30 is reset from "1" to "0".

The entry of the reservation station 33 whose update pending instruction bit has been reset to "0" is deleted at an appropriate timing. At this time, as described with reference to FIG. 2, the data of the corresponding register update buffer address is sent from the register update buffer 25 to the general purpose register 26, and the content of the general purpose register 26 is updated to the data. At the same time, the register update buffer 2
5, the register update buffer address is input to the comparator 23, and the update buffer address table 2
9 is compared with each address. When a coincident address is obtained, the update pending instruction bit in the register update pending table 28 corresponding to that address is reset from "1" to "0".

As described above, when the general-purpose register 26 is updated with reference to the update table 22 (when the update pending instruction bit is "0"), the general-purpose register 2
The data of No. 6 is input to the computing unit 35. On the other hand, when the update pending instruction bit is "1", the data in the general-purpose register 26 has not been updated, and thus cannot be used for the operation. Therefore, data is input to the integrator 35 from the register update buffer 25 storing the update data of the general-purpose register 26.

When an update instruction for the general-purpose register 26 is issued, the data is updated from the register update buffer 25 to the general-purpose register 26, and the update reservation instruction bits of the reservation station 33 and the corresponding entry of the update table 22 are set. Reset to “0”.
Thus, the logic configuration of the instruction control device can be simplified and the number of logic stages can be reduced, so that the machine cycle can be shortened, the clock frequency of the instruction control device 10 can be increased, and the processing speed can be increased. Can be.

FIG. 4 is a diagram showing the configuration of the update table 22 and the reservation station 33. FIG.
(A) is a diagram showing the configuration of the update table 22, where 0
An update buffer address table 29 having up to 15 entries and a register update pending table 28 are shown. Note that 0 to 15 correspond to general-purpose register addresses (general-purpose register numbers).

The update buffer address table 29 is for registering the address of the register update buffer 25 in correspondence with the general-purpose register address, and the register update suspension table 28 is for registering the corresponding general-purpose register 2.
In this case, an update hold instruction bit indicating whether the update of the address No. 6 has been performed or held is registered. For example, if the update pending bit is “0”, it indicates that the corresponding general-purpose register 26 has been updated, so that data is input from the general-purpose register 26 to the arithmetic unit 35 and the update pending bit is set to “0”. If it is "1", the update of the corresponding general purpose register is suspended, so that the data is read from the register update buffer 25 and the arithmetic unit 35 is made to input the data.

Each entry of the update buffer address table 29 and each entry of the register update pending table 28 correspond to each other, and are provided by the number of general-purpose register addresses. In the case of FIG.
, A plurality of general-purpose registers 26
Although the numbers (represented by one block in FIG. 3) are described, it is of course possible to configure the general-purpose register 26 with a memory and register an address where data is recorded. Therefore, hereinafter, the numbers of the general-purpose registers 26 and the general-purpose register addresses have the same meaning.

FIG. 4B is a diagram showing the configuration of the reservation station 33. In each entry of the reservation station 33, a general-purpose register address, a register update buffer address, and an update pending instruction bit are registered corresponding to each general-purpose register address.

An entry is registered in the reservation station 33 when the update pending instruction bit of the update table 22 is "1", that is, when data is to be read from the register update buffer 25 because the general-purpose register 26 has not been updated. The corresponding entry of the update table 22 is registered in the reservation station 33.

Each entry of the reservation station 33 indicates that an instruction using the address of the entry has been issued.
In No. 3, there is provided a function of adding a priority as to which entry is to be executed with higher priority by a mechanism (not shown). Each address registered in the reservation station 33 is input to the reservation station 33 in the order output from the instruction register 20 according to the program. Control to execute from. This priority adding function corresponds to an out-of-order instruction control.

FIG. 5 is a circuit diagram of the comparator 2 shown in FIGS.
It is a figure which shows the specific structure of 3,34. FIG. 5 (a)
This is a configuration for resetting the update pending instruction bit of the update table 22. Update buffer address table 29
Are connected to take out the corresponding update buffer address from each of the entries 0 to 15, and one of the comparators 50-1 to 50-16 provided with the update buffer address corresponding to each general-purpose register address. Input to the terminal.

The other terminals of the comparators 50-1 to 50-16 are configured to receive the register update buffer address from the register update buffer 25, respectively. Since the register update buffer address sent from the register update buffer 25 is the address at which data has been updated from the register update buffer 25 to the general-purpose register 26, the update pending instruction bit of the register update pending table 28 is updated. There is a need.

According to the configuration of FIG. 5A, each of the update buffer addresses in the update buffer address table 29 is compared with the register update buffer address from the register update buffer 25, and the comparator 5 that detects a match is compared.
0-1 to 50-16 are configured to output a reset signal.

The outputs of the comparators 50-1 to 50-16 are connected to the corresponding update pending instruction bit columns in the register update pending table 29, and the reset signals are output from the comparators 50-1 to 50-16. Then, the corresponding update pending instruction bit is reset. Thus, the comparators 50-1 to 50-1
A plurality of update buffer addresses 50-16 are provided, each of which compares the update buffer address of an individual entry of the update buffer address table 29 with the register update buffer address sent from the register update buffer 25, thereby enabling the update buffer address and Since the comparison processing can be performed in parallel, the comparison processing and the reset of the update suspension instruction bit can be performed at high speed.

FIG. 5B shows a configuration for resetting the update pending instruction bit of each entry in the column 30 of the reservation station 33. FIG. 5B shows only the register update buffer address and the update pending instruction bit in the configuration of the reservation station 33. As shown in FIG. 5A, each comparator 51
A connection for acquiring the register update buffer address of each of the entries 0 to 7 is connected to one terminal of -1 to 51-8.

The other terminal of each of the comparators 51-1 to 51-8 receives the register update buffer address from the register update buffer 25. , A reset signal is output for the entry of the reservation station 33 whose coincidence with the register update buffer address is obtained, and the update pending instruction bit of the entry is reset. For this purpose, the outputs of the comparators 51-1 to 51-8 are connected to update pending instruction bits of each entry of the reservation station 33.

As in FIG. 5A, the register update buffer address output from the register update buffer 25 is compared with the register update buffer address of each entry of the reservation station 33 by parallel processing. Can be reset, so that the processing can be performed at high speed.

Next, the register renaming technique according to the present embodiment will be described. FIG. 6 is a diagram illustrating an example of the instruction control device according to the present embodiment. FIG. 6 shows an instruction register 20, an update table 22, a control storage 12a,
A reservation station 33 is shown.

The logical register address is supplied from the instruction register 20 to the update table 22. At this time, in the update table 22, the update buffer address table 29 and the register update pending table 28 are indexed, and the corresponding information P and UBA are read. On the other hand, a signal for selecting an update buffer address and a signal for specifying an update buffer address are sent from the control storage 12a to the gate, and the address specified from the update buffer address table 29 and the control storage 12a is selected. Registered in the station 33.

A signal indicating an update suspension instruction is sent from the control memory 12a to the gate, and the logical sum of the signal and the signal from the register update suspension table 28 is obtained and registered in the reservation station 33. At the same time, control memory 1
A signal instructing the gate to update the RUB 25 is transmitted from the gate 2 a and registered in the reservation station 33.

Next, the register update buffer will be described. FIG. 7 is a diagram showing an operation example of the RUB 25 according to the present embodiment. FIG. 7 shows a reservation station 33, a computing unit 35, a RUB 25, and a GPR 26.
Are connected in series. From the reservation station 33, the register update buffer address UBA1 and the UBA update instruction WR as destinations are calculated by the arithmetic unit 35.
Sent to The arithmetic unit 35 outputs the RU along with the operation result.
B write address DUBA and write instruction WR are RU
The result is sent to B25, and the calculation result is stored in RUB25. Further, data from the RUB 25 is written to the GPR 26.

Next, the reservation station 33
Will be described. FIG. 8 is a diagram illustrating an example of a control circuit of the reservation station 33 according to the present embodiment. + RSO_UBA1 is the first operand UBA stored in entry 0 of the reservation station. + RUB_DUBA is a write address to RUB. + RUB_WR is an instruction to write to RUB. In comparison, + RSO_UBA1 and + RUB_DU
A signal + RESET_RSO_P1 for resetting the update pending instruction P1 of the entry 0 is generated.

Next, a method of updating the GPR 26 will be described. FIG. 9 is a diagram showing an example of a circuit for allocating a register update buffer address to a general-purpose register update instruction in the present embodiment. Reference numeral 71 denotes a register update buffer address register, which advances the value by one each time one general-purpose register update instruction is executed. 72 is an incrementer, and 76 is an update buffer address table.

Reference numeral 73 denotes an update buffer work table, which holds which register update buffer is allocated for work. 74 is a decoder for decoding the operation code part of the instruction register 20. Decoder 7
4 receives an instruction to update the GPR 26 and generates a control signal for updating the update buffer address table 76. A decoder 75 decodes a register address. The decoder 75 generates a control signal indicating which entry of the update buffer address table 76 is to be updated.

The output of one of the decoders 74 and 75 is stored in the gate of the update buffer address table 76 according to the select signal of the update buffer work table 73. The update buffer work table 73 stores the result obtained by sequentially incrementing the register update buffer address stored in the register update buffer address register 71 by the incrementer 72.

When the control signal of the decoder 74 is selected by the select signal of the update buffer work table 73, the update buffer address of the update buffer address table 76 is updated according to the control signal.
On the other hand, when the control signal of the decoder 75 is selected,
Any entry of the update buffer address table 76 is updated according to the control signal.

The incrementer 72 may be slightly changed. For example, the incrementer 72 is made to indicate from 0 (zero) to 12, and the actual RUB 25 has 0
It is configured to implement from (zero) to 15. Then, from 0 (zero) to 12
RUB 25 is assigned, and 13 to 15 are assigned as working registers, and can be used independently of each other.

Next, the operation of FIG. 9 will be described. 10 and 11 are timing charts for explaining the update operation of the update buffer address table 76. FIG.
In FIG. 11, D indicates a decode cycle, and W indicates a write cycle. First, in FIG. 10, the register 1 of the register update buffer address 71 is updated by a first general-purpose register update instruction (LOAD instruction). 2nd LOAD
With the instruction, the register 2 is updated. At clock 1,
In the first LOAD instruction, GPR (1) is mapped to RUB (1).

At the next clock 2, the number 1 is written to the entry of GPR (1) on the update buffer address table 76. At clock 3, the microinstruction is R
UB (2) is assigned as a working register. In clock 4, GPR (2) is not RUB (2) but RU
B (3).

Next, the description moves to FIG. The incrementer 72 is adjusted so that the value following “12” becomes “0”. In the first LOAD instruction, the register 1 of the register update buffer address register 71 is updated. Second
With the LOAD instruction, the register 2 is updated.

At the clock 1, the first LOAD instruction causes G
PR (1) is mapped to RUB (12). At clock 2, on the update buffer address table 76,
The number 12 is written in the entry of GPR (1). At clock 3, there is no operation on the update buffer address table 76, and at clock 4, GPR (2)
(0). Micro instruction is RUB
(13)-(15) can be used freely.

As described above, according to the present embodiment, the update pending instruction of the operand and the register update buffer address of the operand are stored in the table for each operand, and the update pending instruction and the stored instruction are stored in the table. Performs write control to the reservation station by associating the register update buffer address with the address of the register update buffer and the presence / absence of writing of the instruction execution result.If the update pending instruction written to the reservation station is ON, the register update is performed. The instruction execution result is stored in the buffer according to the address of the register update buffer and whether or not the instruction execution result is written.

As a result, the register update buffer can be used as a work register, so that it is possible to mount the work register in an information processing device that performs register renaming without increasing the amount of hardware.

Further, information indicating that the register update buffer in which data is stored is for work is stored in the reservation station. If the register update buffer is for work, information in the reservation station in which a match is detected is stored. Since the update pending instruction is held in the ON state, the register update buffer can be used as a work register, and the work register can be implemented without increasing the amount of hardware.

A general-purpose register is connected to the subsequent stage of the register update buffer, and when the register update buffer is designated as a work data storage register, the allocation of the register update buffer to an instruction for updating the general-purpose register is suppressed. As a result, the register update buffer can be used as a work register, whereby the work register can be implemented without increasing the amount of hardware.

Further, only a specific number can be designated as a working register address, and when a register update buffer address is allocated to an instruction for updating a general purpose register, a number other than the specific number is allocated. In addition, the register update buffer can be used as a work register, whereby the work register can be mounted without increasing the amount of hardware.

Although the present invention has been described with reference to the embodiments, various modifications are possible within the scope of the present invention, and these are not excluded from the scope of the present invention.

[0078]

As described above, according to the first aspect of the present invention, the instruction update pending instruction and the operand register update buffer address are stored in the table for each operand, and the update stored in the table is stored. Write control to the reservation station is performed by associating the address of the register update buffer with the pending instruction and the register update buffer address, so that the register update buffer can be used as a work register, thereby increasing the amount of hardware. There is an effect that an instruction control device capable of mounting a work register without the need is obtained.

Further, according to the invention of claim 2, claim 1
In the invention, information indicating that the register update buffer storing data is for work is stored in the reservation station, and when the register update buffer is for work, the update in the reservation station in which a match is detected is stored. Since the hold instruction is held in the ON state, the register update buffer can be used as a work register, and the work register can be mounted without increasing the amount of hardware.

According to the invention of claim 3, according to claim 2,
In the present invention, a general-purpose register is connected to the subsequent stage of the register update buffer, and when the register update buffer is designated as a work data storage register, allocation of the register update buffer to an instruction for updating the general-purpose register is suppressed. With this configuration, the register update buffer can be used as a work register, and the work register can be mounted without increasing the amount of hardware.

Further, according to the invention of claim 4, according to claim 2,
In the invention of the present invention, only a specific number can be designated as a work register address, and when a register update buffer address is allocated to an instruction for updating a general purpose register, a non-specific number is allocated. The register update buffer can be used as a work register, whereby the work register can be implemented without increasing the amount of hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overview of an instruction control device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation when updating a GPR in the present embodiment.

FIG. 3 is a diagram illustrating a configuration and operation at the time of register reading in this embodiment.

FIG. 4 is a diagram illustrating a configuration example of an update table and a reservation station in the present embodiment.

FIG. 5 is a diagram illustrating a configuration example of a comparator in the present embodiment.

FIG. 6 is a diagram illustrating a part of a configuration for realizing register renaming according to the present embodiment;

FIG. 7 is a diagram illustrating another part of the configuration for realizing register renaming in the present embodiment.

FIG. 8 is a diagram for explaining another part of the configuration for realizing register renaming in the present embodiment.

FIG. 9 is a diagram illustrating a circuit example in which a register update buffer address is assigned to a general-purpose register update instruction in the present embodiment.

FIG. 10 is a timing chart illustrating an update operation of an update buffer address table in the present embodiment.

FIG. 11 is a timing chart illustrating an update operation of an update buffer address table in the present embodiment.

FIG. 12 is a diagram illustrating the operation of a conventional instruction control device.

FIG. 13 is a diagram illustrating an example of a reservation station.

FIG. 14 is a diagram illustrating another example of the reservation station.

FIG. 15 is a diagram illustrating a load (L) instruction and a compare (C) instruction.

FIG. 16 is a diagram illustrating the contents of an update table.

FIG. 17 is a diagram illustrating an example of a reservation station entry.

[Explanation of symbols]

 12a Control storage 20 Instruction register 22 Update table 23 Comparator 25 RUB 26 GPR 30 Update pending instruction bit 33 Reservation station 35 Operation unit 71 Register update buffer address register 72 Incrementer 73 Update buffer work table 74, 75 Decoder 76 Update buffer address table

Claims (4)

[Claims] 1. A reservation station, a table for storing an operand update pending instruction and an operand register update buffer address for each operand, a register update buffer for storing an instruction execution result, and means for specifying an update buffer address; An instruction control device comprising: means for designating an update suspension instruction; and means for selectively storing the designated output in a reservation station. 2. A general-purpose memory for storing an instruction execution result according to an address of the register update buffer and whether or not an instruction execution result is written, when an update suspension instruction written to the reservation station under the control of the control means is in an off state. A register updating buffer, wherein when the instruction execution is completed, an address for supplying data for updating the designated general-purpose register and the register stored in the reservation station are provided. The update of the designated general-purpose register is completed while the update pending instruction in the reservation station in which the match is detected is turned off by comparing the previous address of the update buffer with the previous address of the update buffer. The information indicating that the buffer is for work is Storage station,
2. The instruction control device according to claim 1, wherein when the register update buffer is for work, an update hold instruction in the reservation station in which a match is detected is held in an ON state. 3. The general-purpose register is connected to a stage subsequent to the register update buffer, and when the register update buffer is designated as a working data storage register, the register update buffer is allocated to an instruction for updating the general-purpose register. 3. The instruction control apparatus according to claim 2, wherein 4. A method in which only a specific number can be designated as the work register address, and when a register update buffer address is allocated to an instruction for updating the general purpose register, a number other than the specific number is allocated. 3. The instruction control device according to claim 2, wherein: