JPH01191265A - Vector operation instruction starting system - Google Patents

Abstract

PURPOSE:To shorten the processing time of a vector operation instruction by completing read of the first element before the execution stage of the vector operation instruction and starting the vector operation at the time of receiving a start command sent in the execution stage of the vector instruction from a scalar unit. CONSTITUTION:In a vector unit VPU2, decoding of a command code and read of the first element from a vector register VR22 are completed based on start information before the start of the vector operation and the vector operation indicated by the command is immediately started at the time of receiving the start command from a scalar unit 1. As the result, decoding of the command code and the read operation of the vector register VR22 which are executed in the vector unit VPU2 in a conventional system are not seen in the vector unit VPU2, thereby improving the performance for short vector processing.

Description

[Detailed Description of the Invention] [Summary] Regarding a vector operation instruction activation method in a vector processing device in which a vector unit starts operation based on activation information from a scalar unit, processing time for vector operation instructions in a vector unit is reduced. The above startup information from the scalar unit to the vector unit is sent in the pipeline before the execution stage of the vector operation instruction, and the vector unit executes the vector operation instruction based on the activation information. Before the execution stage, the operation code is decoded and the vector register (
The vector operation is configured to start when the read of the first element from the scalar unit (VR) is completed and a start command sent from the scalar unit in the execution stage of the vector instruction is received.

[Industrial application field]

The present invention provides, based on the activation information from the scalar unit,
Vector operation instruction starting method in a vector processing device where the vector unit starts operating Figure 3 is a diagram showing the relationship between the processing time of a vector operation instruction and the number of vector elements. It shows the processing time when processing vector operation instructions.

Here, the initial value α of the processing time in the vector unit is
For example, vector length (VL) settings.

This is the time required to transfer vector data from the main memory (MS) to the vector register (VR) (vector processing environment setting time), and this initial value α is required for processing vector operation instructions in the vector unit. Because it is necessary, −
a has a smaller number of vector elements than a scalar unit that performs sequential processing (for example, as shown in the figure,
(number of elements: 10 to 20 or less), it can be seen that processing using a scalar unit is rather faster.

However, in recent programming processes, a source program is written in a high-level language called FORTRAN and then compiled.
At that time, statements that indicate the processing of multiple pieces of data, such as DO loops, in the source program are converted into vector operation instructions, so the data processing system that executes the program converted from the source program into the target program, It consists of a scalar unit and a vector unit. Scalar instructions are executed in the scalar unit, and vector instructions are sent from the scalar unit to the vector unit and executed in the vector unit.

In general, the number of loops in the Do loop statement in the source program varies widely, and typically ranges from several times to several thousand times.

Therefore, when a vector instruction with a small number of vector elements is executed in a vector unit, a phenomenon occurs in which the processing time is longer than that in the scalar unit, as described above.

On the other hand, with the overall improvement in the processing power of recent data processing systems, in vector processing devices in which vector uni-nodes operate by starting from a scalar unit, processing speed decreases when the number of vector elements is small. has become more prominent, and there has been a demand for high-speed processing regardless of the number of vector elements.

[Prior art and problems to be solved by the invention] FIG. 2 is a diagram illustrating a conventional vector operation instruction starting method.

First, in SCARA unit 1, at its D stage,
When each instruction is decoded and recognized as a vector operation instruction, the vector unit I-
Startup information (for example, command code, operand address (VR address), etc.) is sent from the instruction buffer 11 to the vector unit l-(VPU) 2.
At the E2 stage, the operation code is decoded and the vector data is read from the vector register (VR) 2.

Hereinafter, vector calculations are performed at each stage shown.

Generally, the processing time T of a vector operation instruction is calculated by the following formula% formula% Here, Tsu: vector instruction rise time.

TEII: Vector operation throughput vL: Vector length.

And TSLI=TO+TIi:S Here, To: vector instruction decoding and vpu startup time.

Tts: 1 vector operation rise time.

It is.

In the conventional vector processing device shown in FIG.
Although EX+TES is short, TD is long (in this example, for example, 3τ), so when the vector length (VL) becomes small (i.e., short vector processing), the vector unit)
There was a problem that the processing performance of (VPU) 2 was not sufficient.

In order to improve performance in such short vector processing, it is sufficient to shorten T, but the decoding of the vector instruction and activation of the vector unit (VPU) 2 are not shown in this figure. Since the scalar unit 1 executes the instructions as shown in the figure, necessary startup information (for example, command code, operand VR) is required after the vector instruction enters the E1 stage.
Send address, etc.) ■, vector unit) (VPU)
After receiving the activation information (2), decode the command code.

, Since preprocessing necessary for vector operations such as read operation of the vector register (VR) was performed, the previous processing method had the problem that the T0 could not be shortened.

In view of the above conventional drawbacks, the present invention provides a vector processing device in which a vector unit starts operation based on activation information from a scalar unit. The operand VR address) is sent to the vector unit before the execution of the arithmetic stage in the vector unit, and processing such as decoding of the 8-command code in the vector unit is made invisible, thereby shortening T. The purpose of this invention is to provide a method for improving short vector performance.

[Means to solve the problem]

The above problem is solved by a vector operation instruction activation method configured as follows.

(1) Based on the startup information from the SCARA unit,
In the vector processing device where the vector unit starts operating, the above activation information from the scalar unit to the vector unit is sent in the pipeline before the execution stage of the vector operation instruction, and the vector unit processes the activation information based on the activation information. hand,
Before the execution stage of the vector operation instruction, decoding of the operation code and reading of the first element from the vector register (VR) are completed, and the start command sent from the scalar unit at the execution stage of the vector instruction is completed. The vector calculation is configured to start at the time of reception.

(2) In response to the reception of startup information and start commands sent from the SCARA unit, a multi-stage command stack is provided in the vector unit to accept multiple vector operation commands in the vector unit, and the SCARA unit , the activation information, and the start command are issued, the system is configured to start processing the next command without waiting for the completion of the execution.

[Effect]

That is, according to the present invention, in a vector processing device in which a vector unit starts operation based on activation information from a scalar unit, for example, the D stage, before the instruction execution stage (E stage) in the scalar unit,
In the A stage, the minimum information necessary to start the vector unit, such as command code, operation input operand VR address, etc., is transferred to the vector unit (VP
U) and issues only the start command at the beginning of the execution stage (E stage).

In the vector unit (VPU), before starting the vector operation, the decoding of the command code and the read operation of the first element from the vector register (VR) are completed based on the above startup information, and the above operation is completed. The vector calculation specified by the command is started immediately upon receiving the start command from the scalar unit.

As a result, in the vector unit (VPU), command code decoding, which was conventionally executed within the vector unit (VPU), and vector register (VPU)
R) Read operation (that is, the above-mentioned T[1) becomes invisible, so that the performance during similar vector processing can be improved.

By adopting this control method, if an interrupt occurs due to an exception event caused by the previous instruction (for example, a program exception) or an external interrupt from an input/output device, the current vector It is necessary to cancel the processing of the arithmetic instruction, but in the control method of the present invention,
At least, the exception event can be recognized at the C stage of the previous instruction (corresponding to the E1 stage of this instruction), so by issuing a cancel signal from the scalar unit at the second E stage (E2 stage), , the start command on the vector unit (VPU) side can be suppressed, and detection of an operation exception due to an instruction that should not be executed can be suppressed.

In addition, in the present invention, by providing multiple stages of command stacks on the vector unit (vPU) side and configuring it to accept multiple vector operation commands, the scalar unit can wait for the execution result after issuing a command. You can now process the next command without any problems.

As described above, when the vector operation instruction starting method according to the present invention is introduced, the rise time of the vector instruction is improved, and the performance of vector operation processing, particularly short vector processing, can be significantly improved.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram schematically showing an embodiment of the present invention,
D stage in scalar unit 1.

The means for transmitting the startup information (2) to the vector unit (VPU) 2 in the A stage and the means for transmitting the start command in the E1 stage are necessary means for carrying out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the vector operation instruction starting method of the present invention will be explained with reference to FIG.

In this embodiment, vector register (VR) (1
? 2) and a vector operation instruction that stores the operation result with the vector register (VR) (R3) in the vector register (VR) (R1).

In this figure, D, 8, E (El, [2), and C ura are scalar units. First, in scalar unit 1, in the D stage of the vector instruction, the vector unit (VP
tl) 2, a command code and the address ■ of the vector register (VR) (R2) are transmitted to the vector unit (VPU) 2.

Immediately after receiving the activation information (VPU) 2, the command code is decoded by the decoder 21, and R is sent from the vector register (VTI) 22.
1st element of vector elements in 2 registers
lead.

Next, scalar unit 1 transfers the address of the R3 register to the vector unit (VPU) in the A stage of the vector instruction.
) Send a call to 2.

As soon as the vector unit (VPU) 2 receives this information, it reads the first element of the vector elements in the R3 register from the vector register (VR) 22.

Then, at the beginning of the E1 stage of the vector instruction, the scalar unit 1 sends the start command 13. and transmits the R1 address.

As is clear from this figure, in the E1 stage,
Vector unit (VPU) 2 is already in Pect/L/
L/Jister (Vl?) (R2), (VR) (R
3) +7) Since the read has been completed, calculation can be started immediately after the start command 13 is received by the control unit 24.

After that, every 1τ, the next vector element is sequentially read out,
The vector operation is executed in a pipeline.

When the vector instruction activation method according to the present invention is adopted, the decoding of the command code and the read operation of the vector register are executed in advance, but if an exception event occurs due to the previous instruction, at least , Since the occurrence of the exception event can be recognized at the C stage, the cancellation signal ■ based on the occurrence of an interrupt due to the exception event is transmitted at the E2 stage, and the calculation result is sent to the vector register (VR) (R1). It is possible to suppress the storage process and cancel the vector operation instruction without detecting the exception event.

In this figure, the startup information from SCARA unit 1 and the start command transmission route are indicated by dotted lines.
By providing 7 memory 25, vector operation command, operand VR address.

Since multiple start commands can be received, the scalar unit l can start processing the next command after issuing a command without waiting for the completion of its execution.

As a result, the vector operation instruction and the next scalar instruction can be executed in parallel. however,
It is necessary to protect the order of the program. There is a certain processing mode (
For example, in the case of sequential processing mode), it is necessary to avoid using the stack memory 25.

As described above, the present invention provides a vector processing device in which a vector unit starts operation based on activation information from a scalar unit, and a vector instruction decoding process that takes time to process a vector operation instruction, and a vector unit activation time (To ), by transmitting the activation information from the scalar unit to the vector unit (VPU) before the execution stage (E stage) of the vector operation instruction, the command of the vector operation is executed before the execution stage of the vector operation instruction. The decoding of the first vector element from the vector register (Vl?) is completed, and at the beginning of the execution stage of the vector operation instruction, a start command is sent from the scalar unit, and the vector that received the start command is The feature of VPU (VPU) is that it performs calculations immediately.

〔Effect of the invention〕

As described above in detail, the vector operation instruction activation method of the present invention is applicable to the vector processing device in which the vector unit starts operation based on activation information from the scalar unit. Activation information is sent in the pipeline before the execution stage of the vector operation instruction, and in the vector unit, based on the activation information, the operation code is decoded and the vector register (VR ), the vector operation is started when the start command sent in the execution stage of the vector instruction from the scalar unit is received. The rise time of an instruction is improved, and the performance of vector arithmetic processing, particularly short vector processing, can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing an embodiment of the present invention. FIG. 2 is a diagram illustrating a conventional vector operation instruction starting method. FIG. 3 is a diagram showing the relationship between the processing time of a vector operation instruction and the number of vector elements. In the drawing, 1 is a scalar unit, and 11 is an instruction buffer. 12 is the vibe line, 13 is the start command. 2 is a vector unit (VPU). 21 is a decoder. 22 is a vector register (VR). 23 is a calculation section, and 24 is a control section. 25 is stack memory. ■ is startup information, ■ is cancellation signal. are shown respectively.

Claims (2)

[Claims] (1) Startup information from SCARA unit (1) ([1])
In a vector processing device, a vector unit (2) starts operating based on the vector unit (2) from the scalar unit (1).
The above activation information ([1]) is sent in the pipeline before the execution stage of the vector operation instruction, and the vector unit (2) executes the above vector operation instruction based on the activation information ([1]). Before the execution stage, the operation code is decoded and the vector register (VR) (2
When the read of the first element from 2) is completed and the start command (13) sent from the scalar unit (1) at the vector instruction execution stage is received, the vector operation is started. Features a vector operation instruction activation method. (2) In response to receiving the startup information and start command sent from the scalar unit (1), the vector unit (2) has a multi-stage command stack (25
), the vector unit (2) accepts multiple vector operation commands, and the scalar unit (1) processes the next command without waiting for the start information and start command to finish executing. 2. The vector operation instruction activation method according to claim 1.